linux-kernel - Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability

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Date:   Wed, 04 Jan 2023 09:17:41 +0100
From:   "Arnd Bergmann" <arnd@...db.de>
To:     "Conor Dooley" <conor@...nel.org>
Cc:     "Palmer Dabbelt" <palmer@...belt.com>,
        Prabhakar <prabhakar.csengg@...il.com>,
        "Conor.Dooley" <conor.dooley@...rochip.com>,
        "Andrew Jones" <ajones@...tanamicro.com>,
        "Albert Ou" <aou@...s.berkeley.edu>,
        "Anup Patel" <apatel@...tanamicro.com>,
        "Atish Patra" <atishp@...osinc.com>,
        "Biju Das" <biju.das.jz@...renesas.com>,
        devicetree@...r.kernel.org,
        "Geert Uytterhoeven" <geert@...ux-m68k.org>,
        guoren <guoren@...nel.org>,
        "Christoph Hellwig" <hch@...radead.org>,
        Heiko Stübner <heiko@...ech.de>,
        "Jisheng Zhang" <jszhang@...nel.org>,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-riscv@...ts.infradead.org,
        "Magnus Damm" <magnus.damm@...il.com>,
        "Nathan Chancellor" <nathan@...nel.org>,
        "Paul Walmsley" <paul.walmsley@...ive.com>,
        "Philipp Tomsich" <philipp.tomsich@...ll.eu>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>,
        "Rob Herring" <robh+dt@...nel.org>,
        "Samuel Holland" <samuel@...lland.org>, soc@...nel.org,
        "Daire McNamara" <daire.mcnamara@...rochip.com>
Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing
 capability

On Wed, Jan 4, 2023, at 01:00, Conor Dooley wrote:
> On Tue, Jan 03, 2023 at 10:28:19PM +0100, Arnd Bergmann wrote:
>> On Tue, Jan 3, 2023, at 22:04, Conor Dooley wrote:
>> > From: Daire McNamara <daire.mcnamara@...rochip.com>
>> >
>> > SiFive L2 cache controller can flush L2 cache. Expose this capability via
>> > driver.
>> >
>> > Signed-off-by: Daire McNamara <daire.mcnamara@...rochip.com>
>> > [Conor: rebase on top of move to cache subsystem]
>> > Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>> > ---
>> > This commit needs more work, and a way to enable it from errata. I've
>> > not gone and done this as PolarFire SoC has archid etc all set to zero.
>> > So we need to go figure out a workaround for this, before adding in
>> > errata enabling code for this. I've included it here as a second user of
>> > the cache management stuff, since what's currently upstream for the
>> > ccache driver does not do any cache management.
>> > ---
>> >  drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++
>> >  1 file changed, 45 insertions(+)
>> 
>> My feeling here is that the cacheflush code is unrelated to the
>> EDAC code and it should just be a separate file. From what I can
>> tell, all of the existing contents of this file can simply
>> get merged into drivers/edac/sifive_edac.c, with the newly
>> added code becoming a standalone driver.
>
> Sure? I'd like to do that independently of whatever is done for the
> ax45mp CMOs though, don't think it's worth holding up that platform's
> support on me splitting this out.

Right, no need to touch the existing file as part of this series,
it probably just gets in the way of defining a good interface here.

    Arnd