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Message-Id: <20230104083204.1865526-1-michael@walle.cc>
Date: Wed, 4 Jan 2023 09:32:04 +0100
From: Michael Walle <michael@...le.cc>
To: jszhang@...nel.org
Cc: aou@...s.berkeley.edu, conor@...nel.org,
devicetree@...r.kernel.org, gregkh@...uxfoundation.org,
ilpo.jarvinen@...ux.intel.com, jirislaby@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org,
palmer@...belt.com, paul.walmsley@...ive.com, robh+dt@...nel.org,
Michael Walle <michael@...le.cc>
Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Hi,
> + uart0: serial@...02000 {
According to the reference manual of the bl808, this is uart3. Can we also
use that name here?
> + compatible = "bouffalolab,bl808-uart";
> + reg = <0x30002000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&xtal>;
This is a shortcut and is likely to change in the future. The xtal
isn't really connected to the uart block, but instead there is a
clock mux and clock gate in between.
> + status = "disabled";
> + };
Thanks,
-michael
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