linux-kernel - Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability

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Message-Id: <1b7d4caa-2c9c-4aef-81ac-47288d3a652c@app.fastmail.com>
Date:   Wed, 04 Jan 2023 13:18:45 +0100
From:   "Arnd Bergmann" <arnd@...db.de>
To:     "Conor Dooley" <conor@...nel.org>
Cc:     "Palmer Dabbelt" <palmer@...belt.com>,
        Prabhakar <prabhakar.csengg@...il.com>,
        "Conor.Dooley" <conor.dooley@...rochip.com>,
        "Andrew Jones" <ajones@...tanamicro.com>,
        "Albert Ou" <aou@...s.berkeley.edu>,
        "Anup Patel" <apatel@...tanamicro.com>,
        "Atish Patra" <atishp@...osinc.com>,
        "Biju Das" <biju.das.jz@...renesas.com>,
        devicetree@...r.kernel.org,
        "Geert Uytterhoeven" <geert@...ux-m68k.org>,
        guoren <guoren@...nel.org>,
        "Christoph Hellwig" <hch@...radead.org>,
        Heiko Stübner <heiko@...ech.de>,
        "Jisheng Zhang" <jszhang@...nel.org>,
        krzysztof.kozlowski+dt@...aro.org, linux-kernel@...r.kernel.org,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-riscv@...ts.infradead.org,
        "Magnus Damm" <magnus.damm@...il.com>,
        "Nathan Chancellor" <nathan@...nel.org>,
        "Paul Walmsley" <paul.walmsley@...ive.com>,
        "Philipp Tomsich" <philipp.tomsich@...ll.eu>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>,
        "Rob Herring" <robh+dt@...nel.org>,
        "Samuel Holland" <samuel@...lland.org>, soc@...nel.org,
        "Daire McNamara" <daire.mcnamara@...rochip.com>
Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing
 capability

On Wed, Jan 4, 2023, at 12:56, Conor Dooley wrote:
> On Wed, Jan 04, 2023 at 11:19:44AM +0100, Arnd Bergmann wrote:
>> On Wed, Jan 4, 2023, at 10:23, Conor Dooley wrote:
>> I would try to replace both of these indirections and instead
>> handle it all from C code in arch_sync_dma_for_device() directly,
>> for the purpose of readability and maintainability.
>> static inline void dma_cache_clean(void *vaddr, size_t size)
>> {
>>         if (!cache_maint_ops.clean)
>>                zicbom_cache_clean(vaddr, size, riscv_cbom_block_size);
>
> And I figure that this function is effectively a wrapper around ALT_CMO_OP()?
>
>>         else
>>                cache_maint_ops.clean(vaddr, size, riscv_cbom_block_size);
>
> And this one gets registered by the driver using an interface like the
> one I already proposed, just with the cache_maint_ops struct expanded?

Yes, exactly.

> Extrapolating, with these changes having an errata would not even be
> needed in order to do cache maintenance.
> Since the ALT_CMO_OP() version would only be used inside
> zicbom_cache_clean(), assuming I understood correctly, a driver could
> just register cache_maint_ops for a given platform without having to
> muck around with errata.

That is the idea, and ALT_CMO_OP() itself can just go away
as by just putting the inline asm without the alternative into
the zicbom_cache_clean() version, making the THEAD branch yet
another cache_maint_ops instance.

>> which then makes it very clear what the actual code path
>> is, while leaving the zicbom case free of indirect function
>> calls. You can still use a static_branch() to optimize the
>> conditional, but I would try to avoid any extra indirection
>> levels or errata checks.
>
> The other thing that I like about this is we can then remove the various
> calls to ALT_CMO_OP() that are scattered around arch/riscv now & replace
> them with functions that have more understandable names.

I only see them in arch/riscv/mm/dma-noncoherent.c and arch/riscv/mm/pmem.c,
but yes, both of these should just call the new functions, whatever the
calling conventions end up being.

    Arnd