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Message-Id: <20230104180513.1379453-3-conor@kernel.org>
Date: Wed, 4 Jan 2023 18:05:14 +0000
From: Conor Dooley <conor@...nel.org>
To: palmer@...belt.com
Cc: conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
Sudeep Holla <sudeep.holla@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Jonathan Corbet <corbet@....net>, Alex Shi <alexs@...nel.org>,
Yanteng Si <siyanteng@...ngson.cn>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-doc@...r.kernel.org
Subject: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property
From: Conor Dooley <conor.dooley@...rochip.com>
Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
RISC-V has used the generic arch topology code, which provides for
disparate CPU capacities. We never defined a binding to acquire this
information from the DT though, so document the one already used by the
generic arch topology code: "capacity-dmips-mhz".
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6720764e765..2480c2460759 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -114,6 +114,12 @@ properties:
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
+ capacity-dmips-mhz:
+ description:
+ u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
+ DMIPS/MHz, relative to highest capacity-dmips-mhz
+ in the system.
+
required:
- riscv,isa
- interrupt-controller
--
2.39.0
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