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Message-ID: <Y7agecsIPC0r/OXB@gmail.com>
Date: Thu, 5 Jan 2023 11:03:37 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Guo Ren <guoren@...nel.org>
Cc: Waiman Long <longman@...hat.com>, peterz@...radead.org,
linux-kernel@...r.kernel.org, Guo Ren <guoren@...ux.alibaba.com>,
Boqun Feng <boqun.feng@...il.com>,
Will Deacon <will@...nel.org>, Ingo Molnar <mingo@...hat.com>
Subject: Re: [PATCH] locking/qspinlock: Optimize pending state waiting for
unlock
* Guo Ren <guoren@...nel.org> wrote:
> On Thu, Jan 5, 2023 at 4:19 AM Ingo Molnar <mingo@...nel.org> wrote:
> >
> >
> > * Guo Ren <guoren@...nel.org> wrote:
> >
> > > > >> The situation is the SMT scenarios in the same core. Not an entering
> > > > >> low-power state situation. Of course, the granularity between cores is
> > > > >> "cacheline", but the granularity between SMT hw threads of the same
> > > > >> core could be "byte" which internal LSU handles. For example, when a
> > > > >> hw-thread yields the resources of the core to other hw-threads, this
> > > > >> patch could help the hw-thread stay in the sleep state and prevent it
> > > > >> from being woken up by other hw-threads xchg_tail.
> > > > >>
> > > > >> Finally, from the software semantic view, does the patch make it more
> > > > >> accurate? (We don't care about the tail here.)
> > > > >
> > > > > Thanks for the clarification.
> > > > >
> > > > > I am not arguing for the simplification part. I just want to clarify
> > > > > my limited understanding of how the CPU hardware are actually dealing
> > > > > with these conditions.
> > > > >
> > > > > With that, I am fine with this patch. It would be nice if you can
> > > > > elaborate a bit more in your commit log.
> > > > >
> > > > > Acked-by: Waiman Long <longman@...hat.com>
> > > > >
> > > > BTW, have you actually observe any performance improvement with this patch?
> > > Not yet. I'm researching how the hardware could satisfy qspinlock
> > > better. Here are three points I concluded:
> > > 1. Atomic forward progress guarantee: Prevent unnecessary LL/SC
> > > retry, which may cause expensive bus transactions when crossing the
> > > NUMA nodes.
> > > 2. Sub-word atomic primitive: Enable freedom from interference
> > > between locked, pending, and tail.
> > > 3. Load-cond primitive: Prevent processor from wasting loop
> > > operations for detection.
> >
> > As to this patch, please send a -v2 version of this patch that has this
> > discussion & explanation included in the changelog, as requested by Waiman.
> Done
>
> https://lore.kernel.org/lkml/20230105021952.3090070-1-guoren@kernel.org/
Applied to tip:locking/core for a v6.3 merge, thanks!
Ingo
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