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Message-ID: <3b6ec431-70ac-cf68-6f46-9dc0affb1e68@sholland.org>
Date: Thu, 5 Jan 2023 08:38:36 -0600
From: Samuel Holland <samuel@...lland.org>
To: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
Cc: Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Maxime Ripard <mripard@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-media@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-staging@...ts.linux.dev,
linux-sunxi@...ts.linux.dev
Subject: Re: [PATCH 4/4] riscv: dts: allwinner: d1: Add video engine node
Hi Paul,
On 1/5/23 04:11, Paul Kocialkowski wrote:
> On Sat 31 Dec 22, 10:46, Samuel Holland wrote:
>> D1 contains a video engine which is supported by the Cedrus driver.
>
> Does it work "outside the box" without power domain management?
> If not, it might be a bit confusing to add the node at this point.
Yes, it does. All of the power domains are enabled by default. However,
if the PPU series is merged first, I will respin this to include the
power-domains property from the beginning.
Regards,
Samuel
>> Signed-off-by: Samuel Holland <samuel@...lland.org>
>> ---
>>
>> arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
>> index dff363a3c934..4bd374279155 100644
>> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
>> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
>> @@ -34,6 +34,17 @@ soc {
>> #address-cells = <1>;
>> #size-cells = <1>;
>>
>> + ve: video-codec@...e000 {
>> + compatible = "allwinner,sun20i-d1-video-engine";
>> + reg = <0x1c0e000 0x2000>;
>> + interrupts = <SOC_PERIPHERAL_IRQ(66) IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_VE>,
>> + <&ccu CLK_VE>,
>> + <&ccu CLK_MBUS_VE>;
>> + clock-names = "ahb", "mod", "ram";
>> + resets = <&ccu RST_BUS_VE>;
>> + };
>> +
>> pio: pinctrl@...0000 {
>> compatible = "allwinner,sun20i-d1-pinctrl";
>> reg = <0x2000000 0x800>;
>> --
>> 2.37.4
>>
>
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