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Date: Tue, 10 Jan 2023 18:56:05 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: linux-arm-msm@...r.kernel.org, andersson@...nel.org,
agross@...nel.org, krzysztof.kozlowski@...aro.org
Cc: marijn.suijten@...ainline.org,
angelogioacchino.delregno@...labora.com,
Konrad Dybcio <konrad.dybcio@...aro.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v8 5/5] arm64: dts: qcom: msm8998: Configure CPRh
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
Now that the CPR v3/v4/Hardened is ready, enable it on MSM8998.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
[Konrad: separate from adding cpufreq, sort nodes and use lowercase hex]
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 325 ++++++++++++++++++++++++++
1 file changed, 325 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index af29a4bfd109..84f73484441f 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -139,6 +139,9 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -153,6 +156,9 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU2: cpu@2 {
@@ -163,6 +169,9 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU3: cpu@3 {
@@ -173,6 +182,9 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu_gold_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
};
CPU4: cpu@100 {
@@ -183,6 +195,9 @@ CPU4: cpu@100 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -197,6 +212,9 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
CPU6: cpu@102 {
@@ -207,6 +225,9 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
CPU7: cpu@103 {
@@ -217,6 +238,9 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
+ operating-points-v2 = <&cpu_silver_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
};
cpu-map {
@@ -310,6 +334,65 @@ scm {
};
};
+ cpu_gold_opp_table: opp-table-gold {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cpu_silver_opp_table: opp-table-silver {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cprh_opp_table: opp-table-cprh {
+ compatible = "operating-points-v2-qcom-level";
+
+ cprh_opp1: opp1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ };
+
+ cprh_opp2: opp2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ };
+
+ cprh_opp3: opp3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <2 3>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -839,6 +922,174 @@ qfprom: qfprom@...000 {
#address-cells = <1>;
#size-cells = <1>;
+ cpr_efuse_speedbin: speedbin@133 {
+ reg = <0x133 0x8>;
+ bits = <5 3>;
+ };
+
+ cpr_fuse_revision: cpr_fusing_rev@13e {
+ reg = <0x13e 0x1>;
+ bits = <3 3>;
+ };
+
+ /* CPR Ring Oscillator: Power Cluster */
+ cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 {
+ reg = <0x218 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 {
+ reg = <0x218 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 {
+ reg = <0x219 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 {
+ reg = <0x219 0x1>;
+ bits = <4 4>;
+ };
+
+ /* CPR Init Voltage: Power Cluster */
+ cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a {
+ reg = <0x21a 0x1>;
+ bits = <0 6>;
+ };
+
+ cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a {
+ reg = <0x21a 0x1>;
+ bits = <6 6>;
+ };
+
+ cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b {
+ reg = <0x21b 0x1>;
+ bits = <4 6>;
+ };
+
+ cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c {
+ reg = <0x21c 0x1>;
+ bits = <2 6>;
+ };
+
+ /* CPR Target Quotients: Power Cluster */
+ cpr_quot3_pwrcl: quot3_pwrcl@21d {
+ reg = <0x21d 0x2>;
+ bits = <6 12>;
+ };
+
+ cpr_quot2_pwrcl: quot2_pwrcl@21f {
+ reg = <0x21f 0x2>;
+ bits = <2 11>;
+ };
+
+ cpr_quot1_pwrcl: quot1_pwrcl@220 {
+ reg = <0x220 0x2>;
+ bits = <6 12>;
+ };
+
+ cpr_quot0_pwrcl: quot0_pwrcl@222 {
+ reg = <0x222 0x2>;
+ bits = <2 12>;
+ };
+
+ /* CPR Quotient Offsets: Power Cluster */
+ cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 {
+ reg = <0x226 0x1>;
+ bits = <1 7>;
+ };
+
+ cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 {
+ reg = <0x227 0x1>;
+ bits = <0 7>;
+ };
+
+ cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 {
+ reg = <0x227 0x1>;
+ bits = <7 6>;
+ };
+
+ /* CPR Ring Oscillator: Performance Cluster */
+ cpr_ro_sel3_perfcl: rosel3_perfcl@229 {
+ reg = <0x229 0x1>;
+ bits = <6 4>;
+ };
+
+ cpr_ro_sel2_perfcl: rosel2_perfcl@22a {
+ reg = <0x22a 0x1>;
+ bits = <2 4>;
+ };
+
+ cpr_ro_sel1_perfcl: rosel1_perfcl@22a {
+ reg = <0x22a 0x1>;
+ bits = <6 4>;
+ };
+
+ cpr_ro_sel0_perfcl: rosel0_perfcl@22b {
+ reg = <0x22b 0x1>;
+ bits = <2 4>;
+ };
+
+ /* CPR Init Voltage: Performance Cluster */
+ cpr_init_voltage3_perfcl: ivolt3_perfcl@22b {
+ reg = <0x22b 0x1>;
+ bits = <6 6>;
+ };
+
+ cpr_init_voltage2_perfcl: ivolt2_perfcl@22c {
+ reg = <0x22c 0x1>;
+ bits = <4 6>;
+ };
+
+ cpr_init_voltage1_perfcl: ivolt1_perfcl@22d {
+ reg = <0x22d 0x1>;
+ bits = <2 6>;
+ };
+
+ cpr_init_voltage0_perfcl: ivolt0_perfcl@22e {
+ reg = <0x22e 0x1>;
+ bits = <0 6>;
+ };
+
+ /* CPR Target Quotients: Performance Cluster */
+ cpr_quot3_perfcl: quot3_perfcl@22f {
+ reg = <0x22f 0x2>;
+ bits = <4 11>;
+ };
+
+ cpr_quot2_perfcl: quot2_perfcl@231 {
+ reg = <0x231 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_quot1_perfcl: quot1_perfcl@232 {
+ reg = <0x232 0x2>;
+ bits = <4 12>;
+ };
+
+ cpr_quot0_perfcl: quot0_perfcl@234 {
+ reg = <0x234 0x2>;
+ bits = <0 12>;
+ };
+
+ /* CPR Quotient Offsets: Performance Cluster */
+ cpr_quot_offset3_perfcl: qoff3_perfcl@237 {
+ reg = <0x237 0x1>;
+ bits = <7 6>;
+ };
+
+ cpr_quot_offset2_perfcl: qoff2_perfcl@238 {
+ reg = <0x238 0x1>;
+ bits = <6 7>;
+ };
+
+ cpr_quot_offset1_perfcl: qoff1_perfcl@239 {
+ reg = <0x239 0x1>;
+ bits = <5 3>;
+ };
+
qusb2_hstx_trim: hstx-trim@23a {
reg = <0x23a 0x1>;
bits = <0 4>;
@@ -2998,6 +3249,80 @@ frame@...28000 {
};
};
+ apc_cprh: power-controller@...c8000 {
+ compatible = "qcom,msm8998-cprh", "qcom,cprh";
+ reg = <0x0179c4000 0x4000>, <0x0179c8000 0x4000>;
+ clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "ref";
+ operating-points-v2 = <&cprh_opp_table>;
+ #power-domain-cells = <1>;
+
+ nvmem-cells = <&cpr_efuse_speedbin>,
+ <&cpr_fuse_revision>,
+ <&cpr_quot0_pwrcl>,
+ <&cpr_quot1_pwrcl>,
+ <&cpr_quot2_pwrcl>,
+ <&cpr_quot3_pwrcl>,
+ <&cpr_quot_offset1_pwrcl>,
+ <&cpr_quot_offset2_pwrcl>,
+ <&cpr_quot_offset3_pwrcl>,
+ <&cpr_init_voltage0_pwrcl>,
+ <&cpr_init_voltage1_pwrcl>,
+ <&cpr_init_voltage2_pwrcl>,
+ <&cpr_init_voltage3_pwrcl>,
+ <&cpr_ro_sel0_pwrcl>,
+ <&cpr_ro_sel1_pwrcl>,
+ <&cpr_ro_sel2_pwrcl>,
+ <&cpr_ro_sel3_pwrcl>,
+ <&cpr_quot0_perfcl>,
+ <&cpr_quot1_perfcl>,
+ <&cpr_quot2_perfcl>,
+ <&cpr_quot3_perfcl>,
+ <&cpr_quot_offset1_perfcl>,
+ <&cpr_quot_offset2_perfcl>,
+ <&cpr_quot_offset3_perfcl>,
+ <&cpr_init_voltage0_perfcl>,
+ <&cpr_init_voltage1_perfcl>,
+ <&cpr_init_voltage2_perfcl>,
+ <&cpr_init_voltage3_perfcl>,
+ <&cpr_ro_sel0_perfcl>,
+ <&cpr_ro_sel1_perfcl>,
+ <&cpr_ro_sel2_perfcl>,
+ <&cpr_ro_sel3_perfcl>;
+ nvmem-cell-names = "cpr_speed_bin",
+ "cpr_fuse_revision",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_quotient4",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_quotient_offset4",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_init_voltage4",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_ring_osc4",
+ "cpr1_quotient1",
+ "cpr1_quotient2",
+ "cpr1_quotient3",
+ "cpr1_quotient4",
+ "cpr1_quotient_offset2",
+ "cpr1_quotient_offset3",
+ "cpr1_quotient_offset4",
+ "cpr1_init_voltage1",
+ "cpr1_init_voltage2",
+ "cpr1_init_voltage3",
+ "cpr1_init_voltage4",
+ "cpr1_ring_osc1",
+ "cpr1_ring_osc2",
+ "cpr1_ring_osc3",
+ "cpr1_ring_osc4";
+ };
+
intc: interrupt-controller@...00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000>, /* GICD */
--
2.39.0
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