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Message-ID: <0cb01d4a-884e-0ee3-120e-b2df92b92a15@arm.com>
Date: Tue, 10 Jan 2023 12:18:35 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Rob Herring <robh@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
Marc Zyngier <maz@...nel.org>,
James Morse <james.morse@....com>,
Alexandru Elisei <alexandru.elisei@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Oliver Upton <oliver.upton@...ux.dev>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>
Cc: Mark Brown <broonie@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvmarm@...ts.linux.dev, linux-perf-users@...r.kernel.org,
James Clark <james.clark@....com>
Subject: Re: [PATCH v4 1/8] perf: arm_spe: Use feature numbering for
PMSEVFR_EL1 defines
On 1/10/23 00:56, Rob Herring wrote:
> Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for
> PMU and SPE revisions") use feature numbering instead of architecture
> versions for the PMSEVFR_EL1 Res0 defines.
>
> Tested-by: James Clark <james.clark@....com>
> Signed-off-by: Rob Herring <robh@...nel.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@....com>
> ---
> v4:
> - Rebase on v6.2-rc1
> v3:
> - No change
> v2:
> - New patch
> ---
> arch/arm64/include/asm/sysreg.h | 6 +++---
> drivers/perf/arm_spe_pmu.c | 4 ++--
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 1312fb48f18b..c4ce16333750 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -273,11 +273,11 @@
> #define SYS_PMSFCR_EL1_ST_SHIFT 18
>
> #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
> -#define SYS_PMSEVFR_EL1_RES0_8_2 \
> +#define PMSEVFR_EL1_RES0_IMP \
> (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
> BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
> -#define SYS_PMSEVFR_EL1_RES0_8_3 \
> - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
> +#define PMSEVFR_EL1_RES0_V1P1 \
> + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
>
> #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
> #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
> index 00e3a637f7b6..65cf93dcc8ee 100644
> --- a/drivers/perf/arm_spe_pmu.c
> +++ b/drivers/perf/arm_spe_pmu.c
> @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver)
> {
> switch (pmsver) {
> case ID_AA64DFR0_EL1_PMSVer_IMP:
> - return SYS_PMSEVFR_EL1_RES0_8_2;
> + return PMSEVFR_EL1_RES0_IMP;
> case ID_AA64DFR0_EL1_PMSVer_V1P1:
> /* Return the highest version we support in default */
> default:
> - return SYS_PMSEVFR_EL1_RES0_8_3;
> + return PMSEVFR_EL1_RES0_V1P1;
> }
> }
>
>
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