linux-kernel - RE: [PATCH v3 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2

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Message-ID: <50178BB5-4698-4A52-AD89-7235C3802411@kernel.org>
Date:   Tue, 10 Jan 2023 07:37:29 +0000
From:   Conor Dooley <conor@...nel.org>
To:     JiaJie Ho <jiajie.ho@...rfivetech.com>
CC:     Olivia Mackall <olivia@...enic.com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Conor Dooley <conor.dooley@...rochip.com>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>
Subject: RE: [PATCH v3 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2



On 10 January 2023 00:59:58 GMT, JiaJie Ho <jiajie.ho@...rfivetech.com> wrote:
>
>
>> -----Original Message-----
>> From: Conor Dooley <conor@...nel.org>
>> Sent: 10 January, 2023 2:02 AM
>> To: JiaJie Ho <jiajie.ho@...rfivetech.com>
>> Cc: Olivia Mackall <olivia@...enic.com>; Herbert Xu
>> <herbert@...dor.apana.org.au>; Rob Herring <robh+dt@...nel.org>;
>> Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Emil Renner
>> Berthing <kernel@...il.dk>; Conor Dooley <conor.dooley@...rochip.com>;
>> linux-crypto@...r.kernel.org; devicetree@...r.kernel.org; linux-
>> kernel@...r.kernel.org; linux-riscv@...ts.infradead.org
>> Subject: Re: [PATCH v3 3/3] riscv: dts: starfive: Add TRNG node for VisionFive
>> 2
>> 
>> Hey folks,
>> 
>> On Tue, Jan 10, 2023 at 12:52:49AM +0800, Jia Jie Ho wrote:
>> > Adding StarFive TRNG controller node to VisionFive 2 SoC.
>> >
>> > Co-developed-by: Jenny Zhang <jenny.zhang@...rfivetech.com>
>> > Signed-off-by: Jenny Zhang <jenny.zhang@...rfivetech.com>
>> > Signed-off-by: Jia Jie Ho <jiajie.ho@...rfivetech.com>
>> > ---
>> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>> >  1 file changed, 10 insertions(+)
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 4ac159d79d66..3c29e0bc6246 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -455,5 +455,15 @@ uart5: serial@...20000 {
>> >  			reg-shift = <2>;
>> >  			status = "disabled";
>> >  		};
>> > +
>> > +		rng: rng@...0c000 {
>> > +			compatible = "starfive,jh7110-trng";
>> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
>> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
>> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
>> 
>> Which clock source is this? I see syscrg and aoncrg in the v3
>> devicetree:
>> https://lore.kernel.org/linux-riscv/20221220011247.35560-7-
>> hal.feng@...rfivetech.com/
>> 
>> Have a missed a patchset which adds support for this particular clock
>> controller? At the very least, I don't think one has reached the linux-riscv
>> mailing list.
>> The clock driver patchset only has aoncrg & syscrg:
>> https://lore.kernel.org/linux-riscv/20221220005054.34518-1-
>> hal.feng@...rfivetech.com/
>> 
>
>Hi Conor,
>
>Thanks for reviewing the patches.
>Yes, the patch for stg domain hasn't been submitted yet.
>In this case should I drop this patch from the series until the related patches reach the mailing list?

Since it doesn't apply anyway, no harm keeping it IMO.
Having the dts can make it easier, although not in this case, to look at the binding and driver.
Just mention it in the cover letter if/when you send another version.

Thanks,
Conor.