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Message-ID: <87y1qahh51.fsf@BL-laptop>
Date: Tue, 10 Jan 2023 10:29:30 +0100
From: Gregory CLEMENT <gregory.clement@...tlin.com>
To: Chris Packham <Chris.Packham@...iedtelesis.co.nz>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"pierre.gondois@....com" <pierre.gondois@....com>,
"vadym.kochan@...ision.eu" <vadym.kochan@...ision.eu>
Cc: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: marvell: AC5/AC5X: Fix address for UART1
Chris Packham <Chris.Packham@...iedtelesis.co.nz> writes:
> Hi All,
>
> On 15/12/22 15:54, Chris Packham wrote:
>> The correct address offset is 0x12100.
>>
>> Fixes: 31be791e26cf ("arm64: dts: marvell: Add UART1-3 for AC5/AC5X")
>> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
>> ---
>> Not sure how this happened. I only noticed when I had a conflict in some
>> local patches I was rebasing against upstream. So I obviously had it
>> right at one point but then managed to break it in the process of
>> cleaning things up for submission.
>
> I know people have probably been away with various holidays but I think
> it's been long enough so....
>
> ping?
Applied on mvebu/fixes
Thanks,
Gregory
>
>>
>> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
>> index 7308f7b6b22c..8bce64069138 100644
>> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
>> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
>> @@ -98,7 +98,7 @@ uart0: serial@...00 {
>>
>> uart1: serial@...00 {
>> compatible = "snps,dw-apb-uart";
>> - reg = <0x11000 0x100>;
>> + reg = <0x12100 0x100>;
>> reg-shift = <2>;
>> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> reg-io-width = <1>;
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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