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Message-ID: <74de50ac-6b10-a268-06f0-70a498e8b42d@intel.com>
Date:   Wed, 11 Jan 2023 14:29:20 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     Kim Phillips <kim.phillips@....com>, x86@...nel.org
Cc:     Borislav Petkov <bp@...en8.de>,
        Borislav Petkov <borislav.petkov@....com>,
        Boris Ostrovsky <boris.ostrovsky@...cle.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
        Joao Martins <joao.m.martins@...cle.com>,
        Jonathan Corbet <corbet@....net>,
        Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        David Woodhouse <dwmw@...zon.co.uk>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Juergen Gross <jgross@...e.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Tony Luck <tony.luck@...el.com>,
        Tom Lendacky <thomas.lendacky@....com>,
        Alexey Kardashevskiy <aik@....com>, kvm@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 6/7] x86/cpu: Support AMD Automatic IBRS

On 1/10/23 14:46, Kim Phillips wrote:
> The AMD Zen4 core supports a new feature called Automatic IBRS.
> 
> It is a "set-and-forget" feature that means that, like
> Intel's Enhanced IBRS, h/w manages its IBRS mitigation
> resources automatically across CPL transitions.

This looks a *LOT* better than what was here before.  Sharing the eibrs
boot options looks great.  Thanks,

Acked-by: Dave Hansen <dave.hansen@...ux.intel.com>

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