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Message-Id: <20230111093245.318745-2-milkfafa@gmail.com>
Date: Wed, 11 Jan 2023 17:32:43 +0800
From: Marvin Lin <milkfafa@...il.com>
To: krzysztof.kozlowski@...aro.org, robh+dt@...nel.org, bp@...en8.de,
tony.luck@...el.com, james.morse@....com, mchehab@...nel.org,
rric@...nel.org, benjaminfair@...gle.com, yuenn@...gle.com,
venture@...gle.com, avifishman70@...il.com, tmaimon77@...il.com,
tali.perry1@...il.com
Cc: linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, openbmc@...ts.ozlabs.org,
KWLIU@...oton.com, YSCHU@...oton.com, ctcchien@...oton.com,
kflin@...oton.com, Marvin Lin <milkfafa@...il.com>
Subject: [PATCH v18 1/3] ARM: dts: nuvoton: Add node for NPCM memory controller
Add node for memory controller present on Nuvoton NPCM SoCs. The
memory controller supports single bit error correction and double bit
error detection.
Signed-off-by: Marvin Lin <milkfafa@...il.com>
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index c7b5ef15b716..d875e8ac1e09 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -179,6 +179,13 @@ fiux: spi@...01000 {
status = "disabled";
};
+ mc: memory-controller@...24000 {
+ compatible = "nuvoton,npcm750-memory-controller";
+ reg = <0xf0824000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
--
2.34.1
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