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Message-Id: <20230111093245.318745-3-milkfafa@gmail.com>
Date: Wed, 11 Jan 2023 17:32:44 +0800
From: Marvin Lin <milkfafa@...il.com>
To: krzysztof.kozlowski@...aro.org, robh+dt@...nel.org, bp@...en8.de,
tony.luck@...el.com, james.morse@....com, mchehab@...nel.org,
rric@...nel.org, benjaminfair@...gle.com, yuenn@...gle.com,
venture@...gle.com, avifishman70@...il.com, tmaimon77@...il.com,
tali.perry1@...il.com
Cc: linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, openbmc@...ts.ozlabs.org,
KWLIU@...oton.com, YSCHU@...oton.com, ctcchien@...oton.com,
kflin@...oton.com, Marvin Lin <milkfafa@...il.com>,
Rob Herring <robh@...nel.org>
Subject: [PATCH v18 2/3] dt-bindings: memory-controllers: nuvoton: Add NPCM memory controller
Add dt-bindings document for Nuvoton NPCM memory controller.
Signed-off-by: Marvin Lin <milkfafa@...il.com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
.../nuvoton,npcm-memory-controller.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml
new file mode 100644
index 000000000000..ac1a5a17749d
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM Memory Controller
+
+maintainers:
+ - Marvin Lin <kflin@...oton.com>
+ - Stanley Chu <yschu@...oton.com>
+
+description: |
+ The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
+ check).
+
+ The memory controller supports single bit error correction, double bit error
+ detection (in-line ECC in which a section (1/8th) of the memory device used to
+ store data is used for ECC storage).
+
+ Note, the bootloader must configure ECC mode for the memory controller.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-memory-controller
+ - nuvoton,npcm845-memory-controller
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mc: memory-controller@...24000 {
+ compatible = "nuvoton,npcm750-memory-controller";
+ reg = <0xf0824000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.34.1
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