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Message-ID: <18134850-da17-80c5-1f83-203db571b63b@kernel.org>
Date: Wed, 11 Jan 2023 11:48:20 +0200
From: Roger Quadros <rogerq@...nel.org>
To: Sinthu Raja <sinthu.raja@...tralsolutions.com>,
Vinod Koul <vkoul@...nel.org>,
Ravi Gunasekaran <r-gunasekaran@...com>,
Siddharth Vadapalli <s-vadapalli@...com>
Cc: Vignesh Raghavendra <vigneshr@...com>,
linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
Sinthu Raja <sinthu.raja@...com>
Subject: Re: [PATCH V2 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if
typec-dir-gpios not specified
On 06/01/2023 09:17, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@...com>
>
> It's possible that the Type-C plug orientation on the DIR line will be
> implemented through hardware design. In that situation, there won't be
> an external GPIO line available, but the driver still needs to address
> this since the DT won't use the typec-dir-gpios property.
>
> Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
> specified in DT.
>
> Signed-off-by: Sinthu Raja <sinthu.raja@...com>
Reviewed-by: Roger Quadros <rogerq@...nel.org>
> ---
>
> Changes in V2:
> =============
> Address review comments:
> - Update commit description as per review comments.
> - Restore code to check only debounce delay only if typec-dir-gpios property is specified in DT.
> - Rename lane_phy_reg variable as master_lane_num.
> - Update inline comments.
>
> V1: https://lore.kernel.org/lkml/20221213124854.3779-2-sinthu.raja@ti.com/T/#mb1f9f8d26b4ef735bbbc3994a1e9c16d52ca2c19
>
> drivers/phy/ti/phy-j721e-wiz.c | 39 +++++++++++++++++++++++++---------
> 1 file changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index ddce5ef7711c..571f0ca18874 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -376,6 +376,7 @@ struct wiz {
> struct gpio_desc *gpio_typec_dir;
> int typec_dir_delay;
> u32 lane_phy_type[WIZ_MAX_LANES];
> + u32 master_lane_num[WIZ_MAX_LANES];
> struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
> struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
> struct clk_onecell_data clk_data;
> @@ -1234,15 +1235,31 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> struct wiz *wiz = dev_get_drvdata(dev);
> int ret;
>
> - /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
> - if (id == 0 && wiz->gpio_typec_dir) {
> - if (wiz->typec_dir_delay)
> - msleep_interruptible(wiz->typec_dir_delay);
> -
> - if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
> - regmap_field_write(wiz->typec_ln10_swap, 1);
> - else
> - regmap_field_write(wiz->typec_ln10_swap, 0);
> + if (id == 0) {
> + /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
> + if (wiz->gpio_typec_dir) {
> + if (wiz->typec_dir_delay)
> + msleep_interruptible(wiz->typec_dir_delay);
> +
> + if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
> + regmap_field_write(wiz->typec_ln10_swap, 1);
> + else
> + regmap_field_write(wiz->typec_ln10_swap, 0);
> + } else {
> + /* if no typec-dir gpio was specified and PHY type is
> + * USB3 with master lane number is '0', set LN10 SWAP
> + * bit to '1'
> + */
> + u32 num_lanes = wiz->num_lanes;
> + int i;
> +
> + for (i = 0; i < num_lanes; i++) {
> + if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3)
> + && wiz->master_lane_num[i] == 0) {
> + regmap_field_write(wiz->typec_ln10_swap, 1);
> + }
> + }
> + }
> }
>
> if (id == 0) {
> @@ -1386,8 +1403,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
> dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
> reg, reg + num_lanes - 1, phy_type);
>
> - for (i = reg; i < reg + num_lanes; i++)
> + for (i = reg; i < reg + num_lanes; i++) {
> + wiz->master_lane_num[i] = reg;
> wiz->lane_phy_type[i] = phy_type;
> + }
> }
>
> return 0;
--
cheers,
-roger
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