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Message-ID: <20230112043812.150393-4-jiajie.ho@starfivetech.com>
Date: Thu, 12 Jan 2023 12:38:12 +0800
From: Jia Jie Ho <jiajie.ho@...rfivetech.com>
To: Olivia Mackall <olivia@...enic.com>,
Herbert Xu <herbert@...dor.apana.org.au>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor.dooley@...rochip.com>
CC: <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: [PATCH v4 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
Adding StarFive TRNG controller node to VisionFive 2 SoC.
Co-developed-by: Jenny Zhang <jenny.zhang@...rfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@...rfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4ac159d79d66..3c29e0bc6246 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -455,5 +455,15 @@ uart5: serial@...20000 {
reg-shift = <2>;
status = "disabled";
};
+
+ rng: rng@...0c000 {
+ compatible = "starfive,jh7110-trng";
+ reg = <0x0 0x1600C000 0x0 0x4000>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "ahb";
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ interrupts = <30>;
+ };
};
};
--
2.25.1
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