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Message-ID: <1673513501-29938-1-git-send-email-quic_mojha@quicinc.com>
Date: Thu, 12 Jan 2023 14:21:41 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Mukesh Ojha <quic_mojha@...cinc.com>
Subject: [PATCH 1/2] arm64: dts: qcom: sm8450: Add TCSR halt register space
Add TCSR register space and refer it from scm node, so that
it can be used by SCM driver.
Signed-off-by: Mukesh Ojha <quic_mojha@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 5704750..e0fa733 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -270,6 +270,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8450", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
#reset-cells = <1>;
};
@@ -1986,6 +1987,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@...0000 {
+ compatible = "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
usb_1_hsphy: phy@...3000 {
compatible = "qcom,sm8450-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.7.4
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