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Message-ID: <12255cf7-eacb-3bf0-db47-d81238f97ba2@microchip.com>
Date:   Thu, 12 Jan 2023 09:49:02 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <Mihai.Sain@...rochip.com>, <Nicolas.Ferre@...rochip.com>,
        <alexandre.belloni@...tlin.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: at91: add support in soc driver for new SAMA7G54
 SiPs

On 05.12.2022 09:01, Mihai Sain wrote:
> Add detection of new SAMA7G54 System-In-Package (SIP) by the SoC driver:
> SAMA7G54D1G, SAMA7G54D2G, SAMA7G54D4G.
> 
> Signed-off-by: Mihai Sain <mihai.sain@...rochip.com>

Applied to at91-soc, thanks!

> ---
>  drivers/soc/atmel/soc.c | 9 +++++++++
>  drivers/soc/atmel/soc.h | 3 +++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
> index dae8a2e0f745..cc9a3e107479 100644
> --- a/drivers/soc/atmel/soc.c
> +++ b/drivers/soc/atmel/soc.c
> @@ -235,6 +235,15 @@ static const struct at91_soc socs[] __initconst = {
>  	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
>  		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
>  		 "sama7g54", "sama7g5"),
> +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D1G_EXID_MATCH,
> +		 "SAMA7G54 1Gb DDR3L SiP", "sama7g5"),
> +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D2G_EXID_MATCH,
> +		 "SAMA7G54 2Gb DDR3L SiP", "sama7g5"),
> +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D4G_EXID_MATCH,
> +		 "SAMA7G54 4Gb DDR3L SiP", "sama7g5"),
>  #endif
>  	{ /* sentinel */ },
>  };
> diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
> index 2ecaa75b00f0..7a9f47ce85fb 100644
> --- a/drivers/soc/atmel/soc.h
> +++ b/drivers/soc/atmel/soc.h
> @@ -70,6 +70,9 @@ at91_soc_init(const struct at91_soc *socs);
>  #define SAMA7G52_EXID_MATCH		0x2
>  #define SAMA7G53_EXID_MATCH		0x1
>  #define SAMA7G54_EXID_MATCH		0x0
> +#define SAMA7G54_D1G_EXID_MATCH		0x00000018
> +#define SAMA7G54_D2G_EXID_MATCH		0x00000020
> +#define SAMA7G54_D4G_EXID_MATCH		0x00000028
>  
>  #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
>  #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0

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