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Message-ID: <7b7cd84a-e9ff-b2c1-4bf0-0ed05cca76bd@amd.com>
Date: Thu, 12 Jan 2023 09:31:43 -0600
From: Tom Lendacky <thomas.lendacky@....com>
To: Pierre Gondois <pierre.gondois@....com>,
linux-kernel@...r.kernel.org
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Florian Fainelli <f.fainelli@...il.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
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Tsahee Zidenberg <tsahee@...apurnalabs.com>,
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Brijesh Singh <brijeshkumar.singh@....com>,
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Jerome Brunet <jbrunet@...libre.com>,
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Subject: Re: [PATCH v2 02/23] arm64: dts: Update cache properties for amd
On 11/7/22 09:56, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
Acked-by: Tom Lendacky <thomas.lendacky@....com>
> ---
> arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> index 93688a0b6820..9f2d983e082d 100644
> --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
> @@ -163,38 +163,47 @@ CPU7: cpu@301 {
> };
>
> L2_0: l2-cache0 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_1: l2-cache1 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_2: l2-cache2 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L2_3: l2-cache3 {
> + compatible = "cache";
> cache-size = <0x100000>;
> cache-line-size = <64>;
> cache-sets = <1024>;
> cache-unified;
> + cache-level = <2>;
> next-level-cache = <&L3>;
> };
>
> L3: l3-cache {
> + compatible = "cache";
> cache-level = <3>;
> cache-size = <0x800000>;
> cache-line-size = <64>;
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