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Message-ID: <f271900f-0d39-0221-9b6e-d6de1a44a363@linaro.org>
Date:   Thu, 12 Jan 2023 16:44:55 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Bjorn Andersson <quic_bjorande@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Johan Hovold <johan+linaro@...nel.org>
Subject: Re: [PATCH] arm64: dts: qcom: sc8280xp: Use MMCX for all DP
 controllers



On 12.01.2023 14:50, Bjorn Andersson wrote:
> While MDSS_GDSC is a subdomain of MMCX, Linux does not respect this
> relationship and sometimes invokes sync_state on the rpmhpd (MMCX)
> before the DisplayPort controller has had a chance to probe.
> 
> The result when this happens is that the power is lost to the multimedia
> subsystem between the probe of msm_drv and the DisplayPort controller -
> which results in an irrecoverable state.
> 
> While this is an implementation problem, this aligns the power domain
> setting of the one DP instance with that of all the others.
> 
> Fixes: 57d6ef683a15 ("arm64: dts: qcom: sc8280xp: Define some of the display blocks")
> Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
> ---
One day we'll hopefully finally overcome this parent-child mess..

Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>

Konrad
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 4f4353f84cba..4511fd939c91 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -2533,7 +2533,7 @@ mdss0_dp3: displayport-controller@...0000 {
>  				interrupts = <15>;
>  				phys = <&mdss0_dp3_phy>;
>  				phy-names = "dp";
> -				power-domains = <&dispcc0 MDSS_GDSC>;
> +				power-domains = <&rpmhpd SC8280XP_MMCX>;
>  
>  				assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
>  						  <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;

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