linux-kernel - [PATCH 3/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 13 Jan 2023 21:30:10 +0530
From:   Poovendhan Selvaraj <quic_poovendh@...cinc.com>
To:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <lee@...nel.org>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <shawnguo@...nel.org>, <arnd@...db.de>,
        <marcel.ziswiler@...adex.com>, <dmitry.baryshkov@...aro.org>,
        <nfraprado@...labora.com>, <broonie@...nel.org>,
        <robimarko@...il.com>, <quic_gurus@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
        <quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
        <quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
        <quic_devipriy@...cinc.com>
Subject: [PATCH 3/5] firmware: scm: Modify only the DLOAD bit in TCSR register for download mode

Add support to read-modify-write TCSR register to modify only DLOAD bit.

Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
Co-developed-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
---
 drivers/firmware/qcom_scm.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index cdbfe54c8146..b56d8f465f71 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -400,7 +400,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
 }
 EXPORT_SYMBOL(qcom_scm_set_remote_state);
 
-static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
+static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable)
 {
 	struct qcom_scm_desc desc = {
 		.svc = QCOM_SCM_SVC_BOOT,
@@ -410,7 +410,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
 		.owner = ARM_SMCCC_OWNER_SIP,
 	};
 
-	desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
+	desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
 
 	return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 }
@@ -419,15 +419,19 @@ static void qcom_scm_set_download_mode(bool enable)
 {
 	bool avail;
 	int ret = 0;
+	u32 dload_addr_val;
 
 	avail = __qcom_scm_is_call_available(__scm->dev,
 					     QCOM_SCM_SVC_BOOT,
 					     QCOM_SCM_BOOT_SET_DLOAD_MODE);
+	ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val);
+
 	if (avail) {
-		ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
+		ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable);
 	} else if (__scm->dload_mode_addr) {
 		ret = qcom_scm_io_writel(__scm->dload_mode_addr,
-				enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
+				enable ? dload_addr_val |
+					QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
 	} else {
 		dev_err(__scm->dev,
 			"No available mechanism for setting download mode\n");
-- 
2.17.1