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Message-ID: <CAMT+MTToR+0_CmVBuGfLemALUv1XuevObAMB=TQXV0Vd7HdW5Q@mail.gmail.com>
Date:   Fri, 13 Jan 2023 21:25:08 +0300
From:   Sasha Finkelstein <fnkl.kernel@...il.com>
To:     Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>
Cc:     thierry.reding@...il.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, marcan@...can.st,
        sven@...npeter.dev, alyssa@...enzweig.io, asahi@...ts.linux.dev,
        linux-arm-kernel@...ts.infradead.org, linux-pwm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 2/5] pwm: Add Apple PWM controller

On Wed, 11 Jan 2023 at 02:06, Uwe Kleine-König
<u.kleine-koenig@...gutronix.de> wrote:
> > + * Limitations:
> > + * - The writes to cycle registers are shadowed until a write to
> > + *   the control register.
> > + * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
> > + *   is a constant off signal.
>
> How does the PWM behave with *APPLE_PWM_CTRLAPPLE_PWM_CTRL = 0?
> (typically: drives constant low)
>
APPLE_PWM_CTRL = 0 implies that the APPLE_CTRL_ENABLE bit is set low, which
turns off the pwm signal (constant low). I do not think that it is
necessary to explicitly
specify that case in the comments.

> Can you please rename such that the (maybe new) name for APPLE_PWM_CTRL
> is a prefix for the (maybe new) APPLE_CTRL_ENABLE and the other register
> bit definitions?
To make sure, you want the register named APPLE_PWM_CTRL, and the bits named
APPLE_PWM_CTRL_ENABLE, APPLE_PWM_CTRL_MODE and so on?

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