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Message-ID: <SA1PR11MB6734571ED95606FD753D0A4AA8C29@SA1PR11MB6734.namprd11.prod.outlook.com>
Date:   Fri, 13 Jan 2023 18:26:16 +0000
From:   "Li, Xin3" <xin3.li@...el.com>
To:     Ingo Molnar <mingo@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "brgerst@...il.com" <brgerst@...il.com>,
        "Bae, Chang Seok" <chang.seok.bae@...el.com>,
        "Gross, Jurgen" <jgross@...e.com>
Subject: RE: [PATCH v6 0/5] x86: Enable LKGS instruction

> > > > LKGS instruction is introduced with Intel FRED (flexible return
> > > > and event delivery) specification. As LKGS is independent of FRED,
> > > > we enable it as a standalone CPU feature.
> > > >
> > > > LKGS behaves like the MOV to GS instruction except that it loads
> > > > the base address into the IA32_KERNEL_GS_BASE MSR instead of the
> > > > GS segment’s descriptor cache, which is exactly what Linux kernel
> > > > does to load user level GS base.  Thus, with LKGS, there is no
> > > > need to SWAPGS away from the kernel GS base.
> > >
> > > Ok, this looks good to me.
> > >
> > > I've applied the first 4 patches to tip:x86/cpu, as the instruction
> > > exists in a public document and these patches are fine stand-alone
> > > as well, such as the factoring out of load_gs_index() methods from a
> > > high-use low level header into a new header file.
> > >
> > > Planning to apply the final, LKGS enabler patch as well, unless
> > > there's any objections from others?
> >
> > Nah, I think that thing's bike-shedded to near death. Let's just do it.
> 
> Ok - applied the #5 patch to tip:x86/cpu, for a v6.3 merge.
> 
> Thanks,
> 
> 	Ingo

Thanks a lot!
Xin

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