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Message-ID: <20230113060133.9394-8-yong.wu@mediatek.com>
Date: Fri, 13 Jan 2023 14:01:30 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Joerg Roedel <joro@...tes.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>
CC: Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Hans Verkuil <hverkuil@...all.nl>, <nfraprado@...labora.com>,
<linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@...labora.com>,
<mingyuan.ma@...iatek.com>, <yf.wang@...iatek.com>,
<libo.kang@...iatek.com>, Yunfei Dong <yunfei.dong@...iatek.com>,
kyrie wu <kyrie.wu@...iatek.corp-partner.google.com>,
<chengci.xu@...iatek.com>, <youlin.pei@...iatek.com>,
<anan.sun@...iatek.com>, Yong Wu <yong.wu@...iatek.com>
Subject: [PATCH 07/10] iommu/mediatek: Add a gap for the iova regions
Currenly masters can not indicate its special dma-ranges. Prepare
for vcodec. some vcodec end address is address + size, if our size
is 4G, the end address may be 0x2_0000_0000. and the
register is u32, then it may get zero. thus add a gap(8M) for
all the regions.
Signed-off-by: Yong Wu <yong.wu@...iatek.com>
---
drivers/iommu/mtk_iommu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e4b8c07d4dbd..dd63d9994133 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -304,15 +304,15 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */
#define for_each_m4u(data, head) list_for_each_entry(data, head, list)
static const struct mtk_iommu_iova_region single_domain[] = {
- {.iova_base = 0, .size = SZ_4G},
+ {.iova_base = 0, .size = SZ_4G - SZ_8M},
};
static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
- { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */
+ { .iova_base = 0x0, .size = SZ_4G - SZ_8M}, /* 0 ~ 4G, 8M as a gap. */
#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
- { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */
- { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */
- { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_8M}, /* 4G ~ 8G */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_8M}, /* 8G ~ 12G */
+ { .iova_base = SZ_4G * 3, .size = SZ_4G - SZ_8M}, /* 12G ~ 16G */
{ .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
{ .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
--
2.18.0
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