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Message-Id: <20230113110738.1505973-2-keguang.zhang@gmail.com>
Date: Fri, 13 Jan 2023 19:07:37 +0800
From: Keguang Zhang <keguang.zhang@...il.com>
To: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Keguang Zhang <keguang.zhang@...il.com>
Subject: [PATCH 1/2] dt-bindings: clock: Add binding for Loongson-1 clock driver
Add devicetree binding document for the Loongson-1 clock driver.
Signed-off-by: Keguang Zhang <keguang.zhang@...il.com>
---
.../bindings/clock/loongson,ls1x-clk.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml
new file mode 100644
index 000000000000..4709c6757f1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 Clock Controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@...il.com>
+
+properties:
+ "#clock-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - loongson,ls1b-clk-pll
+ - loongson,ls1b-clk-cpu
+ - loongson,ls1b-clk-ahb
+ - loongson,ls1c-clk-pll
+ - loongson,ls1c-clk-cpu
+ - loongson,ls1c-clk-ahb
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - "#clock-cells"
+ - compatible
+ - clocks
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33000000>;
+ };
+
+ pll: pll@...78030 {
+ compatible = "loongson,ls1b-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&xtal>;
+ reg = <0x1fe78030 0x4>;
+ };
+
+ cpu_clk: cpu_clk@...78034 {
+ compatible = "loongson,ls1b-clk-cpu";
+ #clock-cells = <0>;
+ clocks = <&pll>;
+ reg = <0x1fe78034 0x4>;
+ };
+
+ ahb_clk: ahb_clk@...78034 {
+ compatible = "loongson,ls1b-clk-ahb";
+ #clock-cells = <0>;
+ clocks = <&pll>;
+ reg = <0x1fe78034 0x4>;
+ };
+
+ apb_clk: apb_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&ahb_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ };
+...
--
2.34.1
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