Message-ID: <MWHPR11MB16938EF0B3FBFB87022A327AEFC19@MWHPR11MB1693.namprd11.prod.outlook.com>
Date:   Mon, 16 Jan 2023 22:48:47 +0000
From:   <Jerry.Ray@...rochip.com>
To:     <linux@...linux.org.uk>
CC:     <andrew@...n.ch>, <f.fainelli@...il.com>, <olteanv@...il.com>,
        <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <jbe@...gutronix.de>,
        <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next v6 6/6] dsa: lan9303: Migrate to PHYLINK

> > > > +static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port,
> > > > +                                  struct phylink_config *config)
> > > > +{
> > > > +     struct lan9303 *chip = ds->priv;
> > > > +
> > > > +     dev_dbg(chip->dev, "%s(%d) entered.", __func__, port);
> > > > +
> > > > +     config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
> > > > +                                MAC_SYM_PAUSE;
> > >
> > > You indicate that pause modes are supported, but...
> > >
> > > > +static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int port,
> > > > +                                     unsigned int mode,
> > > > +                                     phy_interface_t interface,
> > > > +                                     struct phy_device *phydev, int speed,
> > > > +                                     int duplex, bool tx_pause,
> > > > +                                     bool rx_pause)
> > > > +{
> > > > +     u32 ctl;
> > > > +
> > > > +     /* On this device, we are only interested in doing something here if
> > > > +      * this is the xMII port. All other ports are 10/100 phys using MDIO
> > > > +      * to control there link settings.
> > > > +      */
> > > > +     if (port != 0)
> > > > +             return;
> > > > +
> > > > +     ctl = lan9303_phy_read(ds, port, MII_BMCR);
> > > > +
> > > > +     ctl &= ~BMCR_ANENABLE;
> > > > +
> > > > +     if (speed == SPEED_100)
> > > > +             ctl |= BMCR_SPEED100;
> > > > +     else if (speed == SPEED_10)
> > > > +             ctl &= ~BMCR_SPEED100;
> > > > +     else
> > > > +             dev_err(ds->dev, "unsupported speed: %d\n", speed);
> > > > +
> > > > +     if (duplex == DUPLEX_FULL)
> > > > +             ctl |= BMCR_FULLDPLX;
> > > > +     else
> > > > +             ctl &= ~BMCR_FULLDPLX;
> > > > +
> > > > +     lan9303_phy_write(ds, port, MII_BMCR, ctl);
> > >
> > > There is no code here to program the resolved pause modes. Is it handled
> > > internally within the switch? (Please add a comment to this effect
> > > either in get_caps or here.)
> > >
> > > Thanks.
> > >
> >
> > As I look into this, the part does have control flags for advertising
> > Symmetric and Asymmetric pause toward the link partner. The default is set
> > by a configuration strap on power-up. I am having trouble mapping the rx and
> > tx pause parameters into symmetric and asymmetric controls. Where can I find
> > the proper definitions and mappings?
> >
> >   ctl &= ~( ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_AYM);
> >   if(tx_pause)
> >     ctl |= ADVERTISE_PAUSE_CAP;
> >   if(rx_pause)
> >     ctl |= ADVERTISE_PAUSE_AYM;
> 
> lan9303_phylink_mac_link_up() has nothing to do with what might be
> advertised to the link partner - this is called when the link has been
> negotiated and established, and it's purpose is to program the results
> of the resolution into the MAC.
> 
> That means programming the MAC to operate at the negotiated speed and
> duplex, and also permitting the MAC to generate pause frames when its
> receive side becomes full (tx_pause) and whether to act on pause frames
> received over the network (rx_pause).
> 
> If there's nowhere to program the MAC to accept and/or generate pause
> frames, how are they controlled? Does the MAC always accept and/or
> generate them? Or does the MAC always ignore them and never generates
> them?
> 
> If the latter, then that suggests pause frames are not supported, and
> thus MAC_SYM_PAUSE and MAC_ASYM_PAUSE should not be set in the get_caps
> method.
> 
> This leads me on to another question - in the above quoted code, what
> device's BMCR is being accessed in lan9303_phylink_mac_link_up() ? Is
> it a PCS? If it is, please use the phylink_pcs support, as the
> pcs_config() method gives you what is necessary to program the PCS
> advertisement.
> 
> Thanks.
> 
> --

On this device, the XMII connection is the rev-xmii port connected to the CPU.
This is the DSA port. This device 'emulates' a phy (virtual phy) allowing the
CPU to use standard phy registers to set things up.

Let me back up for a moment.
The device supports half-duplex BackPressure as well as full-duplex Flow
Control.
The device has bootstrapping options that will configure the Settings for
BP and FC. On port 0, these strapping options also affect the Virtual Phys
Auto-Negotiation Link Partner Base Page Ability Register.
If auto-negotiation is enabled, the flow control is enabled/disabled based
on the Sym/Asym settings of the Advertised and Link Partner's capabilities
registers.
If Manual Flow Control is enabled, then flow control is programmed into the
Manual_FC_0 register directly and the auto-neg registers are ignored. The
device can be strapped to use (default to) the Manual FC register.

So this is why I'm trying to reflect the flow control settings as provided in
the mac_link_up hook api into the emulated phy's aneg settings.

Question:  In the get capabilities API, should I report the device's
flow control capabilities independent of how the device is bootstrapped or
should I reflect the bootstrapped settings? I consider the bootstrap setting
to affect the register default rather than limit what the device is physically
capable of supporting.

Thanks for helping me get this right.
Regards,
Jerry.

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