lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <6b62b95d-c8e9-527b-934e-b458d2e70d5e@linaro.org>
Date:   Tue, 17 Jan 2023 18:27:46 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Wojciech Zmuda <wzmuda@...vell.com>, linux-kernel@...r.kernel.org
Cc:     jassisinghbrar@...il.com, robh+dt@...nel.org, sgoutham@...vell.com,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v4 2/2] dt-bindings: mailbox: add Marvell MHU

On 17/01/2023 18:16, Wojciech Zmuda wrote:
> Marvell Message Handling Unit is a mailbox controller present in
> Marvell OcteonTx and OcteonTX2 SoC family.
> 
> Signed-off-by: Wojciech Zmuda <wzmuda@...vell.com>
> ---
>  .../bindings/mailbox/marvell,mhu.yaml         | 62 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mailbox/marvell,mhu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/marvell,mhu.yaml b/Documentation/devicetree/bindings/mailbox/marvell,mhu.yaml
> new file mode 100644
> index 000000000000..ace32a437af6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/marvell,mhu.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/marvell,mhu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell Message Handling Unit
> +
> +maintainers:
> +  - Sujeet Baranwal <sbaranwal@...vell.com>
> +  - Sunil Goutham <sgoutham@...vell.com>
> +  - Wojciech Bartczak <wbartczak@...vell.com>
> +
> +description:
> +  The Control-Processors Cluster (CPC) provides Arm-platform specification
> +  entities for managing the system. One of the CPC processors is the System
> +  Control Processor (SCP). The SCP is responsible, among others, for booting
> +  the chip, clock and power initialization, controlling power consumption
> +  through DVFS, monitoring temperature sensors and controlling AVS. The SCP,
> +  as each XCP, contains mailboxes for software-to-software communications.
> +  Mailbox writes cause an interrupt to the local XCP core or to the AP.
> +  This driver exposes AP-SCP Message Handling Unit to the system, providing
> +  the mailbox communication mechanism to the system, with the intention
> +  of plugging into the SCMI framework. It is designed to work with Marvell
> +  OcteonTX and OcteonTX2-based platforms.
> +  Mailbox has no other usage than SCMI communication. In case of
> +  configurations running without SCMI support it should be disabled.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:

This is a friendly reminder during the review process.

It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.

Thank you.


Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ