CPU1             | CPU2           | CPU3
start CS;        |                |
read stage==0    |                |
                 | stage = 1;     |
                 |                |
                 | GP {           |
x = 1;           |                |
                 |                | start CS;
                 |                | read x == 0;
end CS;          |                |
                 | }              |
                 | stage = 2;     |
                 |                | read stage == 2;
                 |                | read x == 1;
                 |                | end CS;