linux-kernel - Re: [PATCH v8 05/28] virt: gunyah: Add hypercalls to identify Gunyah

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Message-ID: <08964d93-8118-1176-c2f8-73e14e022a89@linaro.org>
Date:   Tue, 17 Jan 2023 13:20:53 -0600
From:   Alex Elder <elder@...aro.org>
To:     Elliot Berman <quic_eberman@...cinc.com>,
        Alex Elder <elder@...aro.org>,
        Bjorn Andersson <quic_bjorande@...cinc.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Murali Nalajala <quic_mnalajal@...cinc.com>
Cc:     Trilok Soni <quic_tsoni@...cinc.com>,
        Srivatsa Vaddagiri <quic_svaddagi@...cinc.com>,
        Carl van Schaik <quic_cvanscha@...cinc.com>,
        Prakruthi Deepak Heragu <quic_pheragu@...cinc.com>,
        Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Jonathan Corbet <corbet@....net>,
        Bagas Sanjaya <bagasdotme@...il.com>,
        Jassi Brar <jassisinghbrar@...il.com>,
        Sudeep Holla <sudeep.holla@....com>,
        Mark Rutland <mark.rutland@....com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-acpi@...r.kernel.org
Subject: Re: [PATCH v8 05/28] virt: gunyah: Add hypercalls to identify Gunyah

On 1/10/23 11:56 AM, Elliot Berman wrote:
>> Is there any need for the endianness of these values to be specified?
>> Does Gunyah operate with a well-defined endianness?  Is there any
>> chance a VM can run with an endianness different from Gunyah?  I
>> see that the arm_smcc_* structures are defined without endianness.
>> (Sorry if these are dumb questions.)
>>
> 
> All of the data transfers for hypercalls happen via registers, so 
> endianness doesn't have impact here (there is no "low address" in a 
> register).

I don't believe that is technically true.  Practically speaking,
it's probably almost *always* little-endian.  But for example,
here:

https://developer.arm.com/documentation/102376/0100/Alignment-and-endianness
it says:

     Endianness

     In Armv8-A, instruction fetches are always treated as
     little-endian.

     For data accesses, it is IMPLEMENTATION DEFINED whether
     both little-endian and big-endian are supported. And if
     only one is supported, it is IMPLEMENTATION DEFINED
     which one is supported.

     For processors that support both big-endian and
     little-endian, endianness is configured per Exception
     level.

Perhaps that last sentence doesn't apply to HVC exceptions
but to me it *sounds* like it's at least possible for a VM
to be running with an endianness that differs from the
hypervisor (perhaps not other VMs though.)

This is not an area of expertise of mine, so I would love
for someone who knows more to correct me if I'm wrong.

It's likely to be fine as-is, but (other than the work to
do it and get it right) it doesn't hurt to specify it and
do the conversions as data is passes to/from the hypervisor.

					-Alex