linux-kernel - RE: [PATCH 0/1] perf: fix reset interface potential failure

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Message-ID: <OS3PR01MB9269B2010B90029682F9E78BF3C69@OS3PR01MB9269.jpnprd01.prod.outlook.com>
Date:   Tue, 17 Jan 2023 06:40:46 +0000
From:   "Masahiko Yamada (Fujitsu)" <yamada.masahiko@...itsu.com>
To:     "peterz@...radead.org" <peterz@...radead.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "acme@...nel.org" <acme@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
        "jolsa@...nel.org" <jolsa@...nel.org>,
        "namhyung@...nel.org" <namhyung@...nel.org>
CC:     "linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 0/1] perf: fix reset interface potential failure

Dear all

> There is a potential bug where PERF_EVENT_IOC_RESET
> does not work when accessing PMU registers directly
> from userspace in the perf_event interface.
> 
> In the x86 environment, the kernel(perf_event reset handling) has a
> potential failure, but it works with the papi library side workaround.
> The PMU register direct access feature from user space was implemented in
> the perf_event facility from linux-5.18 version in the arm64 environment,
> but it does not work with the workaround on the papi library side in the
> arm64 environment.
> The workaround worked in the x86 environment and not in the arm64
> environment because in the arm64 environment, only CPU_CYCLES was
> a 64 bit counter and the rest were 32 bit counters, so the workaround
> cleared the upper 32 bits of the value measured by CPU_CYCLES.
> 
> For this reason, we have created a patch on the kernel
> that fixes a potential perf_event reset failure.

I have not received any comments or objections to this patch so far, 
but could you give me any comments on this patch?

Best regards,
Masahiko Yamada