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Message-ID: <5ceeaf13-8073-efe2-7a56-370071ff8b3d@linaro.org>
Date: Wed, 18 Jan 2023 04:11:26 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Abel Vesa <abel.vesa@...aro.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Johan Hovold <johan@...nel.org>
Subject: Re: [PATCH v5 4/6] phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register
offsets
On 18/01/2023 00:41, Abel Vesa wrote:
> The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
> UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets
> in a dedicated header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
> .../phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 30 +++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 2 ++
> 2 files changed, 32 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
--
With best wishes
Dmitry
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