linux-kernel - Re: [PATCH v3 3/8] phy: qcom-qmp: pcs: Add v6.20 register offsets

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Message-ID: <62b5b6d7-312e-9112-b109-4e42f36445a2@linaro.org>
Date:   Wed, 18 Jan 2023 06:25:38 +0200
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Abel Vesa <abel.vesa@...aro.org>, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Johan Hovold <johan@...nel.org>
Subject: Re: [PATCH v3 3/8] phy: qcom-qmp: pcs: Add v6.20 register offsets

On 18/01/2023 02:53, Abel Vesa wrote:
> The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
> PCIE g4x2. Add the new PCS offsets in a dedicated header file.
> 
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 ++++++++++++++++++
>   drivers/phy/qualcomm/phy-qcom-qmp.h           |  2 ++
>   2 files changed, 20 insertions(+)
>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h

I can not verify register offsets, but generally looks good. Thus:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

-- 
With best wishes
Dmitry