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Message-ID: <7eb58e2459715a6b2bb5eb45e2ce1f1e88050dff.camel@microchip.com>
Date: Wed, 18 Jan 2023 09:21:07 +0100
From: Steen Hegelund <steen.hegelund@...rochip.com>
To: Pierre Gondois <pierre.gondois@....com>,
<linux-kernel@...r.kernel.org>
CC: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Florian Fainelli <f.fainelli@...il.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
"Tsahee Zidenberg" <tsahee@...apurnalabs.com>,
Antoine Tenart <atenart@...nel.org>,
Brijesh Singh <brijeshkumar.singh@....com>,
Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
Tom Lendacky <thomas.lendacky@....com>,
"Neil Armstrong" <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Khuong Dinh <khuong@...amperecomputing.com>,
Liviu Dudau <liviu.dudau@....com>,
"Sudeep Holla" <sudeep.holla@....com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
William Zhang <william.zhang@...adcom.com>,
Anand Gore <anand.gore@...adcom.com>,
Kursad Oney <kursad.oney@...adcom.com>,
Rafał Miłecki <rafal@...ecki.pl>,
Alim Akhtar <alim.akhtar@...sung.com>,
Shawn Guo <shawnguo@...nel.org>, Li Yang <leoyang.li@....com>,
Sascha Hauer <s.hauer@...gutronix.de>,
"Pengutronix Kernel Team" <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
"NXP Linux Team" <linux-imx@....com>, Chester Lin <clin@...e.com>,
Andreas Färber <afaerber@...e.de>,
Matthias Brugger <mbrugger@...e.com>,
NXP S32 Linux Team <s32@....com>,
Wei Xu <xuwei5@...ilicon.com>, Chanho Min <chanho.min@....com>,
Andrew Lunn <andrew@...n.ch>,
Gregory Clement <gregory.clement@...tlin.com>,
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<UNGLinuxDriver@...rochip.com>,
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Clark Wang <xiaoning.wang@....com>,
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Vadym Kochan <vadym.kochan@...ision.eu>,
Sameer Pujar <spujar@...dia.com>,
Akhil R <akhilrajeev@...dia.com>,
"Mikko Perttunen" <mperttunen@...dia.com>,
Prathamesh Shete <pshete@...dia.com>,
Sumit Gupta <sumitg@...dia.com>,
Diogo Ivo <diogo.ivo@...nico.ulisboa.pt>,
Vidya Sagar <vidyas@...dia.com>,
Ashish Mhetre <amhetre@...dia.com>,
"Johan Jonker" <jbx6244@...il.com>,
Christopher Obbard <chris.obbard@...labora.com>,
Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
Aswani Reddy <aswani.reddy@...sung.com>,
Shashank Prashar <s.prashar@...sung.com>,
"Arnd Bergmann" <arnd@...db.de>, <devicetree@...r.kernel.org>,
<linux-rpi-kernel@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-amlogic@...ts.infradead.org>,
<linux-samsung-soc@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <openbmc@...ts.ozlabs.org>,
<linux-tegra@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-realtek-soc@...ts.infradead.org>,
<linux-renesas-soc@...r.kernel.org>,
<linux-rockchip@...ts.infradead.org>
Subject: Re: [PATCH v2 13/23] arm64: dts: Update cache properties for
microchip
Hi Pierre,
This looks good to me.
Reviewed-by: Steen Hegelund <Steen.Hegelund@...rochip.com>
BR
Steen
On Mon, 2022-11-07 at 16:57 +0100, Pierre Gondois wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@....com>
> ---
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 2dd5e38820b1..c4bca23b96b9 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -52,6 +52,7 @@ cpu1: cpu@1 {
> };
> L2_0: l2-cache0 {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> --
> 2.25.1
>
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