| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 18 Jan 2023 13:49:51 +0100
From: Patrick Delaunay <patrick.delaunay@...s.st.com>
To: Alexandre TORGUE <alexandre.torgue@...s.st.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Arnd Bergmann <arnd@...db.de>
CC: Patrick Delaunay <patrick.delaunay@...s.st.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>
Subject: [PATCH] ARM: dts: stm32: Update part number NVMEM description on stm32mp131
The STM32MP13x Device Part Number (also named RPN in reference manual)
only uses the first 12 bits in OTP4, all the other bit are reserved and
they can be different of zero; they must be masked in NVMEM result, so
the number of bits must be defined in the nvmem cell description.
Fixes: 1da8779c0029 ("ARM: dts: stm32: add STM32MP13 SoCs support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@...s.st.com>
---
arch/arm/boot/dts/stm32mp131.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index f50051e81ee3..2f186a0ae92e 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -1233,6 +1233,7 @@ bsec: efuse@...05000 {
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
+ bits = <0 12>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
--
2.25.1
Powered by blists - more mailing lists