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Message-ID: <86v8l2msqk.wl-maz@kernel.org>
Date:   Thu, 19 Jan 2023 15:47:15 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Gavin Shan <gshan@...hat.com>
Cc:     Oliver Upton <oliver.upton@...ux.dev>, kvmarm@...ts.linux.dev,
        kvmarm@...ts.cs.columbia.edu, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, pbonzini@...hat.com, corbet@....net,
        james.morse@....com, suzuki.poulose@....com, yuzenghui@...wei.com,
        catalin.marinas@....com, will@...nel.org, ricarkol@...gle.com,
        eric.auger@...hat.com, yuzhe@...china.com, renzhengeek@...il.com,
        ardb@...nel.org, peterx@...hat.com, seanjc@...gle.com,
        shan.gavin@...il.com
Subject: Re: [PATCH 1/4] KVM: arm64: Allow saving vgic3 LPI pending status in no running vcpu context

On Thu, 19 Jan 2023 01:11:44 +0000,
Gavin Shan <gshan@...hat.com> wrote:
> 
> I will have vgic_write_guest_lock() in v2. Note that those 3 paths can't be
> running in parallel since one switch is shared by them. Alternatively, we
> extend struct vgic_dist::save_tables_in_progress from 'bool' to 'unsigned long'.
> Several bit is defined for each site as below. In this way, the 3 paths can be
> running in parallel:
> 
>   unsigned long struct vgic_dist::save_tables_in_progress
> 
>   #define VGIC_DIST_SAVE_ITS_ITE		0	/* ITS Translation Entry */
>   #define VGIC_DIST_SAVE_ITS_DTE		1	/* ITS Device Table Entry */
>   #define VGIC_DIST_SAVE_ITS_CTE		2	/* ITS Collection Table Entry */
>   #define VGIC_DIST_SAVE_ITS_CT			3	/* ITS Collection Table */
>   #define VGIC_DIST_SAVE_VGIC3_LPI		4	/* VGIC3 LPI Pending Status */
>   #define VGIC_DIST_SAVE_VGIC3_PENDING_TABLE	5	/* VGIC3 Pending Table */
> 
> The drawback is the calls are limited to 64. If those 3 paths can't be running
> in parallel, we needn't the extension at all.

It should all be completely sequential. KVM_DEV_ARM_ITS_SAVE_TABLES
runs in a context where everything is locked, and so is
VGIC_DIST_SAVE_VGIC3_PENDING_TABLE.

	M.

-- 
Without deviation from the norm, progress is not possible.

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