[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230120024445.244345-11-xingyu.wu@starfivetech.com>
Date: Fri, 20 Jan 2023 10:44:44 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>
CC: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
"Paul Walmsley" <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
Xingyu Wu <xingyu.wu@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: [PATCH v1 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.
Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index c60280b89c73..e1d66709207a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -82,6 +82,14 @@ &mclk_ext {
clock-frequency = <12288000>;
};
+&dvp_clk {
+ clock-frequency = <74250000>;
+};
+
+&hdmitx0_pixelclk {
+ clock-frequency = <297000000>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d0d95ef7aa1a..ab0822ce2095 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -233,6 +233,16 @@ mclk_ext: mclk_ext {
#clock-cells = <0>;
};
+ dvp_clk: dvp_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ hdmitx0_pixelclk: hdmitx0_pixelclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
--
2.25.1
Powered by blists - more mailing lists