linux-kernel - Re: [PATCH] perf/x86: KVM: Disable vPMU support on hybrid CPUs (host PMUs)

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Message-ID: <Y8r604tRexxWlF8F@google.com>
Date:   Fri, 20 Jan 2023 20:34:27 +0000
From:   Sean Christopherson <seanjc@...gle.com>
To:     "Liang, Kan" <kan.liang@...ux.intel.com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Jianfeng Gao <jianfeng.gao@...el.com>,
        Andrew Cooper <Andrew.Cooper3@...rix.com>,
        Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH] perf/x86: KVM: Disable vPMU support on hybrid CPUs (host
 PMUs)

On Fri, Jan 20, 2023, Liang, Kan wrote:
> On 2023-01-20 12:32 p.m., Sean Christopherson wrote:
> > On Fri, Jan 20, 2023, Liang, Kan wrote:
> >> There is nothing wrong for the information provided by the kernel. I
> >> think it should be a KVM issue (my guess is the CPUID enumeration.) we
> >> should fix rather than simply disable the PMU for entire hybrid machines.
> > 
> > I'm not arguing this isn't KVM's problem, and I'm all for proper enabling in KVM,
> > but I'm not seeing any patches being posted.  In the meantime, we've got bug reports
> > coming in about KVM guests having PMU problems on hybrid hosts, and a pile of
> > evidence that strongly suggests this isn't going to be fixed by a one-line patch.
> > 
> > Again, I'm not against enabling vPMU on hybrid CPUs, but AFAICT the enabling is
> > non-trivial and may require new uAPI to provide the necessary information to
> > userspace.  As a short term fix, and something that can be backported to stable
> > trees, I don't see a better alternative than disabling vPMU support.
> 
> I just did some tests with the latest kernel on a RPL machine, and
> observed the below error in the guest.
> 
> [    0.118214] unchecked MSR access error: WRMSR to 0x38f (tried to
> write 0x00011000f0000003f) at rIP: 0xffffffff83082124
> (native_write_msr+0x4/0x30)
> [    0.118949] Call Trace:
> [    0.119092]  <TASK>
> [    0.119215]  ? __intel_pmu_enable_all.constprop.0+0x88/0xe0
> [    0.119533]  intel_pmu_enable_all+0x15/0x20
> [    0.119778]  x86_pmu_enable+0x17c/0x320
> 
> 
> The error is caused by the access to an unsupported bit (bit 48).
> The bit is to enable the Perf Metrics feature, which is a p-core only
> feature.
> 
> KVM doesn't support the feature, so the corresponding bit of
> PERF_CAPABILITIES MSR is not exposed to the guest. For a non-hybrid
> platform, guest checks the bit. Everything works well.
> 
> However, the current implementation in perf kernel for ADL and RPL
> doesn't check the bit. Because the bit is not reliable on ADL and RPL.
> Perf assumes that the p-core hardware always has the feature enabled.
> There is no problem for the bare metal, but seems bring troubles on KVM.
> 
> There is no such issue for the later platforms anymore, e.g., MTL, since
> we enhance the PMU features enumeration for the hybrid platforms.
> Please find the enhancement in Chapter 10 NEXT GENERATION PERFORMANCE
> MONITORING UNIT (PMU)
> https://cdrdv2-public.intel.com/671368/architecture-instruction-set-extensions-programming-reference.pdf
> 
> I think, for a short term fix, we should fix the issue in the perf
> kernel for ADL and RPL, rather than disable the entire vPMU on a hybrid
> platform.
> 
> How about the below patch?

No, fudging around this in the guest isn't a viable fix, even as a short term fix.
Linux isn't the only guest supported by KVM, the VMM isn't strictly required to
set HYPERVISOR in guest CPUID, and it doesn't fix the problems with trying to use
microarchitectural events.

> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index dfd2c124cdf8..d667e8b79286 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6459,7 +6459,13 @@ __init int intel_pmu_init(void)
>  					__EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
>  							   0, pmu->num_counters, 0, 0);
>  		pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
> -		pmu->intel_cap.perf_metrics = 1;
> +		/*
> +		 * The perf metrics bit is not reliable on ADL and RPL. For bare
> +		 * metal, it's safe to assume that the feature is always enabled
> +		 * on p-core, but we cannot do the same assumption for KVM.
> +		 */
> +		if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
> +			pmu->intel_cap.perf_metrics = 1;
>  		pmu->intel_cap.pebs_output_pt_available = 0;
> 
>  		memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids,
> sizeof(pmu->hw_cache_event_ids));
> 
> 
> Thanks,
> Kan