[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <A87231FB-5B5D-46B7-9888-5770039B7EA1@zytor.com>
Date: Fri, 20 Jan 2023 12:50:51 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: Andrew Cooper <Andrew.Cooper3@...rix.com>,
Dave Hansen <dave.hansen@...el.com>,
"Li, Xin3" <xin3.li@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"peterz@...radead.org" <peterz@...radead.org>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>
CC: "x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: the x86 sysret_rip test fails on the Intel FRED architecture
On January 20, 2023 10:52:02 AM PST, Andrew Cooper <Andrew.Cooper3@...rix.com> wrote:
>On 20/01/2023 5:45 pm, Dave Hansen wrote:
>> On 1/19/23 23:49, Li, Xin3 wrote:
>>> The x86 sysret_rip test has the following assertion:
>>>
>>> /* R11 and EFLAGS should already match. */
>>> assert(ctx->uc_mcontext.gregs[REG_EFL] ==
>>> ctx->uc_mcontext.gregs[REG_R11]);
>>>
>>> This is being tested to avoid kernel state leak due to sysret vs iret,
>>> but that on FRED r11 is *always* preserved, and the test just fails.
>> Let's figure out the reason that FRED acts differently, first. Right
>> now, the SDM says:
>>
>> SYSCALL also saves RFLAGS into R11
>>
>> so that behavior of SYSCALL _looks_ architectural to me. Was this
>> change in SYSCALL behavior with FRED intentional?
>
>FRED 3.0 Section 7.4 says the only changes for the SYSCALL and SYSENTER
>instructions are the enablement conditions. Nowhere else is there
>mention of a FRED OS needing to emulate legacy syscall behaviour by
>adjusting %r11/%rcx
>
>However, ERETU does handle flags different to SYSRET (in particular, I
>think you can establish TF on the instruction boundary after SYSCALL
>now). What are the raw values of REG_EFL and REG_R11 ?
>
>~Andrew
>
Just to avoid any confusion:
Syscall and sysenter in a FRED system are treated equivalently to software interrupts, e.g. INT 0x80. They do not modify any registers.
Powered by blists - more mailing lists