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Date: Sat, 21 Jan 2023 12:10:03 +0100
From: Johan Jonker <jbx6244@...il.com>
To: linus.walleij@...aro.org, brgl@...ev.pl
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
heiko@...ech.de, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
kever.yang@...k-chips.com, sjg@...omium.org,
philipp.tomsich@...ll.eu, john@...anate.com,
quentin.schulz@...obroma-systems.com
Subject: [PATCH v2 8/8] ARM: dts: rockchip: rk3066a: move gpio nodes to root
The relation between gpio and pinctrl is now described
by the gpio-ranges property. Move rk3066a gpio nodes to root.
Signed-off-by: Johan Jonker <jbx6244@...il.com>
---
arch/arm/boot/dts/rk3066a.dtsi | 159 +++++++++++++++------------------
1 file changed, 72 insertions(+), 87 deletions(-)
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4d7cf6f1b..ac329cf14 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -217,6 +217,18 @@
<150000000>, <75000000>;
};
+ gpio6: gpio@...0a000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x2000a000 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO6>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
timer2: timer@...0e000 {
compatible = "snps,dw-apb-timer";
reg = <0x2000e000 0x100>;
@@ -238,6 +250,18 @@
};
};
+ gpio0: gpio@...34000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x20034000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
timer0: timer@...38000 {
compatible = "snps,dw-apb-timer";
reg = <0x20038000 0x100>;
@@ -254,6 +278,30 @@
clock-names = "timer", "pclk";
};
+ gpio1: gpio@...3c000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x2003c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@...3e000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x2003e000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
tsadc: tsadc@...60000 {
compatible = "rockchip,rk3066-tsadc";
reg = <0x20060000 0x100>;
@@ -266,96 +314,33 @@
status = "disabled";
};
+ gpio3: gpio@...80000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@...84000 {
+ compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio@...34000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x20034000 0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@...3c000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x2003c000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@...3e000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x2003e000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@...80000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x20080000 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@...84000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x20084000 0x100>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio6: gpio@...0a000 {
- compatible = "rockchip,rk3066a-gpio-bank", "rockchip,gpio-bank";
- reg = <0x2000a000 0x100>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO6>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 192 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
pcfg_pull_default: pcfg-pull-default {
bias-pull-pin-default;
--
2.20.1
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