linux-kernel - Re: [PATCH v3 5/8] arm64: dts: qcom: Add msm8939 SoC

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Message-ID: <1d6c5aae-dde8-3780-e851-f304e43d3ddf@linaro.org>
Date:   Sat, 21 Jan 2023 22:57:44 +0000
From:   Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To:     Stephan Gerhold <stephan@...hold.net>
Cc:     agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
        djakov@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-arm-msm@...r.kernel.org,
        linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, benl@...areup.com,
        shawn.guo@...aro.org, fabien.parent@...aro.org, leo.yan@...aro.org,
        dmitry.baryshkov@...aro.org, Jun Nie <jun.nie@...aro.org>,
        James Willcox <jwillcox@...areup.com>,
        Joseph Gates <jgates@...areup.com>,
        Max Chen <mchen@...areup.com>, Zac Crosby <zac@...areup.com>,
        Vincent Knecht <vincent.knecht@...loo.org>
Subject: Re: [PATCH v3 5/8] arm64: dts: qcom: Add msm8939 SoC

On 18/01/2023 09:59, Stephan Gerhold wrote:
> Why are you adding a dummy power domain here? IMO this would be better
> added together with CPR. Especially because I would expect two power
> domains here later ("mx", "cpr"). For cpufreq you also need to make
> votes for the "MSM8939_VDDMX" power domain.

Confirmed power-domain is a required property, dtbs check will complain 
without it.

I'll leave further discussion on the format of CPR for the CPR series 
but our working example supposes the below as a starting point.

I'm not aware of VDDMX in the CPR path but its not at this node.

CPU2: cpu@102 {
     device_type = "cpu";
     compatible = "arm,cortex-a53", "arm,armv8";
     reg = <0x102>;
     next-level-cache = <&L2_1>;
     enable-method = "qcom,kpss-acc-v2";
     qcom,acc = <&acc2>;
     qcom,saw = <&saw2>;
     clocks = <&apcs1>;
     operating-points-v2 = <&cluster1_opp_table>;
     power-domains = <&cpr>;
     power-domain-names = "cpr";
     #cooling-cells = <2>;
     capacity-dmips-mhz = <1024>;
};

cluster1_opp_table: cluster1-opp-table {
     compatible = "operating-points-v2-qcom-cpu";
     opp-shared;

     /* Used by qcom-cpufreq-nvmem.c */
     nvmem-cells = <&cpr_efuse_speedbin_pvs>;
     nvmem-cell-names = "cpr_efuse_speedbin_pvs";

     opp-200000000 {
         opp-hz = /bits/ 64 <200000000>;
         opp-supported-hw = <0x3f>;
         required-opps = <&cpr_opp3>;
     };

     opp-345600000 {
         opp-hz = /bits/ 64 <345600000>;
         opp-supported-hw = <0x3f>;
         required-opps = <&cpr_opp3>;
     };
};

cpr_opp_table: cpr-opp-table {
     compatible = "operating-points-v2-qcom-level";

     cpr_opp1: opp1 {
         opp-hz = /bits/ 64 <200000000>;
             opp-level = <1>;
             qcom,opp-fuse-level = <1>;
         };
     cpr_opp2: opp2 {
         opp-hz = /bits/ 64 <345600000>;
             opp-level = <2>;
             qcom,opp-fuse-level = <1>;
          };
          cpr_opp3: opp3 {
             opp-hz = /bits/ 64 <400000000>;
             opp-level = <3>;
             qcom,opp-fuse-level = <1>;
          };
     };
     /* etc */
};

---
bod