linux-kernel - Re: [PATCH v3 2/5] dt-bindings: i2c: Add hpe,gxp-i2c

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <12428676-2923-4AAD-9963-AA701A2A5E90@hpe.com>
Date:   Mon, 23 Jan 2023 20:05:37 +0000
From:   "Hawkins, Nick" <nick.hawkins@....com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC:     "Verdun, Jean-Marie" <verdun@....com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "joel@....id.au" <joel@....id.au>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 2/5] dt-bindings: i2c: Add hpe,gxp-i2c

> > + hpe,sysreg:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Phandle to a global status and enable registers shared
> > + between each I2C controller instance. Each bit of the
> > + registers represents an individual I2C engine.


> But what is the purpose? What is it doing? Why I2C controller needs it?

Here is an updated to describe the registers' purpose, and function.

description:
Phandle to the global status and enable interrupt registers shared
between each I2C engine controller instance. It enables the I2C
engine controller to act as both a master or slave by being able to
arm and respond to interrupts from its engine. Each bit in the
registers represent the respective bit position.

Thank you for your feedback,

-Nick Hawkins