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Message-ID: <Y87wfaMJ2HLchgap@hirez.programming.kicks-ass.net>
Date:   Mon, 23 Jan 2023 21:39:25 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com
Cc:     mingo@...hat.com, linux-kernel@...r.kernel.org,
        namhyung@...nel.org, eranian@...gle.com, ak@...ux.intel.com,
        Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH] perf/x86/intel/ds: Fix the conversion from TSC to perf
 time

On Mon, Jan 23, 2023 at 09:20:27AM -0800, kan.liang@...ux.intel.com wrote:
> The TSC unstable case seems to be some corner cases (e.g., due to broken
> BIOS). This patch doesn't support the conversion when the TSC is
> unstable. The TSC in a PEBS record will be dropped and fallback to the
> software perf time provided by the generic code.

:-(

You're saying there's modern systems (PEBS timestamps are fairly new)
that trigger unstable TSC ?

What systems in specific have you observed this on -- we really need to
name and shame them, this is fully unacceptable.

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