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Message-ID: <Y85lFD3m5pdpNtdR@linaro.org>
Date: Mon, 23 Jan 2023 12:44:36 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible
On 23-01-22 15:10:59, Krzysztof Kozlowski wrote:
> On 19/01/2023 15:04, Abel Vesa wrote:
> > Add the SM8550 platform to the binding.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > ---
> >
> > The v3 of this patchset is:
> > https://lore.kernel.org/all/20230119112453.3393911-1-abel.vesa@linaro.org/
> >
> > Changes since v3:
> > * renamed noc_aggr to noc_aggr_4, as found in the driver
> >
> > Changes since v2:
> > * dropped the pipe from clock-names
> > * removed the pcie instance number from aggre clock-names comment
> > * renamed aggre clock-names to noc_aggr
> > * dropped the _pcie infix from cnoc_pcie_sf_axi
> > * renamed pcie_1_link_down_reset to simply link_down
> > * added enable-gpios back, since pcie1 node will use it
> >
> > Changes since v1:
> > * Switched to single compatible for both PCIes (qcom,pcie-sm8550)
> > * dropped enable-gpios property
> > * dropped interconnects related properties, the power-domains
> > * properties
> > and resets related properties the sm8550 specific allOf:if:then
> > * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific
> > allOf:if:then clock-names array and decreased the minItems and
> > maxItems for clocks property accordingly
> > * added "minItems: 1" to interconnects, since sm8550 pcie uses just
> > * one,
> > same for interconnect-names
> >
> >
> > .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index a5859bb3dc28..58f926666332 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -34,6 +34,7 @@ properties:
> > - qcom,pcie-sm8250
> > - qcom,pcie-sm8450-pcie0
> > - qcom,pcie-sm8450-pcie1
> > + - qcom,pcie-sm8550
> > - qcom,pcie-ipq6018
> >
> > reg:
> > @@ -65,9 +66,11 @@ properties:
> > dma-coherent: true
> >
> > interconnects:
> > + minItems: 1
> > maxItems: 2
> >
>
> I don't see my concerns from v3 answered.
Check the dates for v4 and your reply to v3.
v4 was sent a day before you sent your v3 comments. :)
>
> This is a friendly reminder during the review process.
>
> It seems my previous comments were not fully addressed. Maybe my
> feedback got lost between the quotes, maybe you just forgot to apply it.
> Please go back to the previous discussion and either implement all
> requested changes or keep discussing them.
Will address your comments in next version.
>
> Thank you.
>
> Best regards,
> Krzysztof
>
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