linux-kernel - Re: [PATCH v4 4/6] phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets

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Message-ID: <Y85n6Z3lPhj6gAKb@linaro.org>
Date:   Mon, 23 Jan 2023 12:56:41 +0200
From:   Abel Vesa <abel.vesa@...aro.org>
To:     Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Johan Hovold <johan@...nel.org>
Subject: Re: [PATCH v4 4/6] phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register
 offsets

On 23-01-17 16:42:07, Dmitry Baryshkov wrote:
> On 17/01/2023 16:20, Abel Vesa wrote:
> > The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
> > UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets
> > in a dedicated header file.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > ---
> >   .../phy-qcom-qmp-qserdes-txrx-ufs-v6.h        | 30 +++++++++++++++++++
> >   drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       |  2 ++
> >   2 files changed, 32 insertions(+)
> >   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > new file mode 100644
> > index 000000000000..6238dd2b8421
> > --- /dev/null
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > @@ -0,0 +1,30 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2023, Linaro Limited
> > + */
> > +
> > +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
> > +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
> > +
> > +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX			0x28
> > +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX			0x2c
> > +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX		0x30
> > +#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX		0x34
> 
> Emty line please
> 

Sure. Will drop in the next version.

> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2			0x08
> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4			0x10
> 
> Any chance to doublecheck these two values? I think that UCDR_FO_GAIN_RATE2
> is 0xd4 (according to phy-qcom-ufs-qmp-v4-cape.h from msm-5.10)

Double checked. The values are correct. Please note that your are
looking in a header file for qmp v4. This is v6.

> 
> > +
> > +#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL			0x178
> > +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0			0x208
> > +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1			0x20c
> > +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3			0x214
> > +#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6			0x220
> > +#define QSERDES_UFS_V6_RX_MODE_RATE2_B3				0x238
> > +#define QSERDES_UFS_V6_RX_MODE_RATE2_B6				0x244
> > +#define QSERDES_UFS_V6_RX_MODE_RATE3_B3				0x25c
> > +#define QSERDES_UFS_V6_RX_MODE_RATE3_B4				0x260
> > +#define QSERDES_UFS_V6_RX_MODE_RATE3_B5				0x264
> > +#define QSERDES_UFS_V6_RX_MODE_RATE3_B8				0x270
> > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B3				0x280
> > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B6				0x28c
> > +
> > +#endif
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > index 110d8fb9309f..a5cdd58c5b4d 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > @@ -27,6 +27,8 @@
> >   #include "phy-qcom-qmp-pcs-ufs-v4.h"
> >   #include "phy-qcom-qmp-pcs-ufs-v5.h"
> > +#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
> > +
> >   /* QPHY_SW_RESET bit */
> >   #define SW_RESET				BIT(0)
> >   /* QPHY_POWER_DOWN_CONTROL */
> 
> -- 
> With best wishes
> Dmitry
>