linux-kernel - Re: [PATCH v4 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes

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Message-ID: <Y86W60Lsh1zyiECF@hovoldconsulting.com>
Date:   Mon, 23 Jan 2023 15:17:15 +0100
From:   Johan Hovold <johan@...nel.org>
To:     Abel Vesa <abel.vesa@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Manivannan Sadhasivam <mani@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and
 controllers nodes

On Mon, Jan 23, 2023 at 03:11:40PM +0200, Abel Vesa wrote:
> On 23-01-23 14:39:55, Abel Vesa wrote:
> > On 23-01-23 09:51:20, Johan Hovold wrote:
> > > On Thu, Jan 19, 2023 at 04:04:52PM +0200, Abel Vesa wrote:
> > > > Add PCIe controllers and PHY nodes.
> > > > 
> > > > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>

> > > > +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> > > > +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > > > +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > > > +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > > > +				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > > > +				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
> > > > +				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
> > > > +			clock-names = "aux",
> > > > +				      "cfg",
> > > > +				      "bus_master",
> > > > +				      "bus_slave",
> > > > +				      "slave_q2a",
> > > > +				      "ddrss_sf_tbu",
> > > 
> > > You're reusing a clock name which doesn't seem to match this SoC. I
> > > don't know what "QTB" refers to here and if it's just some Qualcomm
> > > alternate name for "TBU" which could make this ok.
> > 
> > I'll come back later with an answer here, once I know exactly what QTB
> > means.
> 
> So, AFAICT, they replaced the TBU with QTB, which basically does the
> same thing. It is part of the SMMU. So, yes, it is just an alternate
> name, at least from the clock point of view.

Good, thanks for checking.

Johan