linux-kernel - Re: Internal vs. external barriers (was: Re: Interesting LKMM litmus test)

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Message-ID: <20230124172647.GN2948950@paulmck-ThinkPad-P17-Gen-1>
Date:   Tue, 24 Jan 2023 09:26:47 -0800
From:   "Paul E. McKenney" <paulmck@...nel.org>
To:     Jonas Oberhauser <jonas.oberhauser@...weicloud.com>
Cc:     Andrea Parri <parri.andrea@...il.com>,
        Alan Stern <stern@...land.harvard.edu>,
        Jonas Oberhauser <jonas.oberhauser@...wei.com>,
        Peter Zijlstra <peterz@...radead.org>, will <will@...nel.org>,
        "boqun.feng" <boqun.feng@...il.com>, npiggin <npiggin@...il.com>,
        dhowells <dhowells@...hat.com>,
        "j.alglave" <j.alglave@....ac.uk>,
        "luc.maranget" <luc.maranget@...ia.fr>, akiyks <akiyks@...il.com>,
        dlustig <dlustig@...dia.com>, joel <joel@...lfernandes.org>,
        urezki <urezki@...il.com>,
        quic_neeraju <quic_neeraju@...cinc.com>,
        frederic <frederic@...nel.org>,
        Kernel development list <linux-kernel@...r.kernel.org>
Subject: Re: Internal vs. external barriers (was: Re: Interesting LKMM litmus
 test)

On Tue, Jan 24, 2023 at 05:39:53PM +0100, Jonas Oberhauser wrote:
> 
> 
> On 1/24/2023 5:22 PM, Paul E. McKenney wrote:
> > I clearly recall some
> > store-based lack of ordering after a grace period from some years back,
> > and am thus far failing to reproduce it.
> > 
> > And here is another attempt that herd7 actually does allow.
> > 
> > So what did I mess up this time?  ;-)
> > 
> > 							Thanx, Paul
> > 
> > ------------------------------------------------------------------------
> > 
> > C C-srcu-observed-4
> > 
> > (*
> >   * Result: Sometimes
> >   *
> >   * The Linux-kernel implementation is suspected to forbid this.
> >   *)
> > 
> > {}
> > 
> > P0(int *x, int *y, int *z, struct srcu_struct *s)
> > {
> > 	int r1;
> > 
> > 	r1 = srcu_read_lock(s);
> > 	WRITE_ONCE(*y, 2);
> > 	WRITE_ONCE(*x, 1);
> > 	srcu_read_unlock(s, r1);
> > }
> > 
> > P1(int *x, int *y, int *z, struct srcu_struct *s)
> > {
> > 	int r1;
> > 
> > 	WRITE_ONCE(*y, 1);
> > 	synchronize_srcu(s);
> > 	WRITE_ONCE(*z, 2);
> > }
> > 
> > P2(int *x, int *y, int *z, struct srcu_struct *s)
> > {
> > 	WRITE_ONCE(*z, 1);
> > 	smp_store_release(x, 2);
> > }
> > 
> > exists (x=1 /\ y=1 /\ z=1)
> 
> I think even if you implement the unlock as mb() followed by some store that
> is read by the gp between mb()s, this would still be allowed.

The implementation of synchronize_srcu() has quite a few smp_mb()
invocations.

But exactly how are you modeling this?  As in what additional accesses
and memory barriers are you placing in which locations?

> I have already forgotten the specifics, but I think the power model allows
> certain stores never propagating somewhere?

PowerPC would forbid the 3.2W case, where each process used an
smp_store_release() as its sole ordering (no smp_mb() calls at all).

> If z=2,z=1,x=2 never propagate to P0, you might start by executing P0, then
> P1, and then P2 at which point the memory system decides that x=1 overwrites
> x=2, and the latter simply doesn't propagate anywhere.

This propagation is modulated by the memory barriers, though.

> (I'll let anyone who has the model at hand correct me on this, because I
> have to take a walk now).

Have a good walk!

							Thanx, Paul