linux-kernel - Re: [PATCH v5 1/2] riscv: Get rid of riscv_pfn

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Message-ID: <20230125114044.qcr2canalvljevcu@orel>
Date:   Wed, 25 Jan 2023 12:40:44 +0100
From:   Andrew Jones <ajones@...tanamicro.com>
To:     Alexandre Ghiti <alexghiti@...osinc.com>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>, Guo Ren <guoren@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Frank Rowand <frowand.list@...il.com>,
        Conor Dooley <conor@...nel.org>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arch@...r.kernel.org
Subject: Re: [PATCH v5 1/2] riscv: Get rid of riscv_pfn_base variable

On Wed, Jan 25, 2023 at 09:12:13AM +0100, Alexandre Ghiti wrote:
> Use directly phys_ram_base instead, riscv_pfn_base is just the pfn of
> the address contained in phys_ram_base.
> 
> Even if there is no functional change intended in this patch, actually
> setting phys_ram_base that early changes the behaviour of
> kernel_mapping_pa_to_va during the early boot: phys_ram_base used to be
> zero before this patch and now it is set to the physical start address of
> the kernel. But it does not break the conversion of a kernel physical
> address into a virtual address since kernel_mapping_pa_to_va should only
> be used on kernel physical addresses, i.e. addresses greater than the
> physical start address of the kernel.

afaict, only CONFIG_XIP_KERNEL kernels use phys_ram_base prior to
setup_bootmem() and, for them, this change only redundantly sets
phys_ram_base to the same thing, so I believe this is a no functional
change patch.

> 
> Signed-off-by: Alexandre Ghiti <alexghiti@...osinc.com>
> ---
>  arch/riscv/include/asm/page.h | 3 +--
>  arch/riscv/mm/init.c          | 6 +-----
>  2 files changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> index 9f432c1b5289..728eee53152a 100644
> --- a/arch/riscv/include/asm/page.h
> +++ b/arch/riscv/include/asm/page.h
> @@ -91,8 +91,7 @@ typedef struct page *pgtable_t;
>  #endif
>  
>  #ifdef CONFIG_MMU
> -extern unsigned long riscv_pfn_base;
> -#define ARCH_PFN_OFFSET		(riscv_pfn_base)
> +#define ARCH_PFN_OFFSET		(PFN_DOWN(phys_ram_base))
>  #else
>  #define ARCH_PFN_OFFSET		(PAGE_OFFSET >> PAGE_SHIFT)
>  #endif /* CONFIG_MMU */
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 478d6763a01a..225a7d2b65cc 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -271,9 +271,6 @@ static void __init setup_bootmem(void)
>  #ifdef CONFIG_MMU
>  struct pt_alloc_ops pt_ops __initdata;
>  
> -unsigned long riscv_pfn_base __ro_after_init;
> -EXPORT_SYMBOL(riscv_pfn_base);
> -
>  pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
>  pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
>  static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
> @@ -285,7 +282,6 @@ static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAG
>  
>  #ifdef CONFIG_XIP_KERNEL
>  #define pt_ops			(*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops))
> -#define riscv_pfn_base         (*(unsigned long  *)XIP_FIXUP(&riscv_pfn_base))
>  #define trampoline_pg_dir      ((pgd_t *)XIP_FIXUP(trampoline_pg_dir))
>  #define fixmap_pte             ((pte_t *)XIP_FIXUP(fixmap_pte))
>  #define early_pg_dir           ((pgd_t *)XIP_FIXUP(early_pg_dir))
> @@ -985,7 +981,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
>  	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
>  	kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
>  
> -	riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr);
> +	phys_ram_base = kernel_map.phys_addr;

nit: I'd put this in the #else part of the #ifdef CONFIG_XIP_KERNEL above
to have some consistency with that #ifdef arm and also avoid the redundant
assignment of phys_ram_base for CONFIG_XIP_KERNEL.

>  
>  	/*
>  	 * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit
> -- 
> 2.37.2
>

Otherwise,

Reviewed-by: Andrew Jones <ajones@...tanamicro.com>

Thanks,
drew