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Message-ID: <acbb8d20-2e7e-e38c-9edb-8f8fa203a094@linaro.org>
Date: Fri, 27 Jan 2023 00:12:08 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
linux-arm-msm@...r.kernel.org, andersson@...nel.org,
agross@...nel.org, krzysztof.kozlowski@...aro.org
Cc: marijn.suijten@...ainline.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 2/6] clk: qcom: Add GPU clock controller driver for
SM6125
On 26/01/2023 20:13, Konrad Dybcio wrote:
> Add support for the GPU clock controller found on SM6125.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
> v1 -> v2:
>
> - Add "depends on" (Krzysztof)
With three nits fixed,
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gpucc-sm6125.c | 444 ++++++++++++++++++++++++++++++++
> 3 files changed, 454 insertions(+)
> create mode 100644 drivers/clk/qcom/gpucc-sm6125.c
>
[skipped]
> +static struct clk_branch gpu_cc_gx_gfx3d_clk = {
> + .halt_reg = 0x1054,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x1054,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_gx_gfx3d_clk",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
> + },
parent_hws
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_gfx3d_clk = {
> + .halt_reg = 0x10a4,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x10a4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_gfx3d_clk",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpu_cc_gx_gfx3d_clk.clkr.hw,
> + },
parent_hws
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_gmu_clk = {
> + .halt_reg = 0x1098,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1098,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_gmu_clk",
> + .parent_data = &(const struct clk_parent_data) {
parent_hws
> + .hw = &gpu_cc_gmu_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
> + .halt_reg = 0x108c,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x108c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cx_snoc_dvm_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cxo_aon_clk = {
> + .halt_reg = 0x1004,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cxo_aon_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_cxo_clk = {
> + .halt_reg = 0x109c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x109c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_cxo_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_sleep_clk = {
> + .halt_reg = 0x1090,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1090,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_ahb_clk = {
> + .halt_reg = 0x1078,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x1078,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_ahb_clk",
> + .flags = CLK_IS_CRITICAL,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
> + .halt_reg = 0x5000,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x5000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct gdsc gpu_cx_gdsc = {
> + .gdscr = 0x106c,
> + .gds_hw_ctrl = 0x1540,
> + .pd = {
> + .name = "gpu_cx_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +static struct gdsc gpu_gx_gdsc = {
> + .gdscr = 0x100c,
> + .pd = {
> + .name = "gpu_gx_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +static struct clk_regmap *gpu_cc_sm6125_clocks[] = {
> + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
> + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
> + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
> + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
> + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
> + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
> + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
> + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
> + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
> + [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr,
> + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
> + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
> + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
> + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
> + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
> +};
> +
> +static struct gdsc *gpucc_sm6125_gdscs[] = {
> + [GPU_CX_GDSC] = &gpu_cx_gdsc,
> + [GPU_GX_GDSC] = &gpu_gx_gdsc,
> +};
> +
> +static const struct regmap_config gpu_cc_sm6125_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x9000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gpu_cc_sm6125_desc = {
> + .config = &gpu_cc_sm6125_regmap_config,
> + .clks = gpu_cc_sm6125_clocks,
> + .num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks),
> + .gdscs = gpucc_sm6125_gdscs,
> + .num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs),
> +};
> +
> +static const struct of_device_id gpu_cc_sm6125_match_table[] = {
> + { .compatible = "qcom,sm6125-gpucc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table);
> +
> +static int gpu_cc_sm6125_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + unsigned int value, mask;
> +
> + regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config);
> + clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config);
> +
> + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
> + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
> + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
> + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
> + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, mask, value);
> +
> + /* Set up PERIPH/MEM retain on the GPU core clock */
> + regmap_update_bits(regmap, gpu_cc_gx_gfx3d_clk.halt_reg,
> + (BIT(14) | BIT(13)), (BIT(14) | BIT(13)));
> +
> + return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
> +}
> +
> +static struct platform_driver gpu_cc_sm6125_driver = {
> + .probe = gpu_cc_sm6125_probe,
> + .driver = {
> + .name = "gpucc-sm6125",
> + .of_match_table = gpu_cc_sm6125_match_table,
> + },
> +};
> +
> +static int __init gpu_cc_sm6125_init(void)
> +{
> + return platform_driver_register(&gpu_cc_sm6125_driver);
> +}
> +subsys_initcall(gpu_cc_sm6125_init);
> +
> +static void __exit gpu_cc_sm6125_exit(void)
> +{
> + platform_driver_unregister(&gpu_cc_sm6125_driver);
> +}
> +module_exit(gpu_cc_sm6125_exit);
> +
> +MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
> +MODULE_LICENSE("GPL");
--
With best wishes
Dmitry
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