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Message-ID: <1684cd8a-5766-0bcb-3301-ce517d39c370@collabora.com>
Date: Thu, 26 Jan 2023 09:42:00 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Stephen Boyd <sboyd@...nel.org>, mturquette@...libre.com
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
matthias.bgg@...il.com, edward-jw.yang@...iatek.com,
johnson.wang@...iatek.com, wenst@...omium.org,
miles.chen@...iatek.com, chun-jie.chen@...iatek.com,
rex-bc.chen@...iatek.com, jose.exposito89@...il.com,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
kernel@...labora.com
Subject: Re: [PATCH v1 0/6] MediaTek Frequency Hopping: MT6795/8173/92/95
Il 26/01/23 03:07, Stephen Boyd ha scritto:
> Quoting AngeloGioacchino Del Regno (2022-12-22 07:51:41)
>> This series adds support for Frequency Hopping (FHCTL) on more MediaTek
>> SoCs, specifically, MT6795, MT8173, MT8192 and MT8195.
>>
>> In order to support older platforms like MT6795 and MT8173 it was
>> necessary to add a new register layout that is ever-so-slightly
>> different from the one that was previously introduced for MT8186.
>>
>> Since the new layout refers to older SoCs, the one valid for MT8186
>> and newer SoCs was renamed to be a "v2" layout, while the new one
>> for older chips gets the "v1" name.
>>
>> Note: These commits won't change any behavior unless FHCTL gets
>> explicitly enabled and configured in devicetrees.
>
> Can you resend this? It conflicts with your latest cleanup series.
Right. Sorry about forgetting to update this one - will rebase and
resend today.
Thanks!
Angelo
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