linux-kernel - Re: [net-next 1/3] net: ethernet: adi: adin1110: add PTP clock support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20230126095934.23107-1-alexandru.tachici@analog.com>
Date:   Thu, 26 Jan 2023 11:59:34 +0200
From:   Alexandru Tachici <alexandru.tachici@...log.com>
To:     <andrew@...n.ch>
CC:     <alexandru.tachici@...log.com>, <davem@...emloft.net>,
        <devicetree@...r.kernel.org>, <edumazet@...gle.com>,
        <krzysztof.kozlowski+dt@...aro.org>, <kuba@...nel.org>,
        <lennart@...omain.com>, <linux-kernel@...r.kernel.org>,
        <netdev@...r.kernel.org>, <pabeni@...hat.com>,
        <richardcochran@...il.com>, <robh+dt@...nel.org>,
        <weiyongjun1@...wei.com>, <yangyingliang@...wei.com>
Subject: Re: [net-next 1/3] net: ethernet: adi: adin1110: add PTP clock support

> > +static int adin1110_enable_perout(struct adin1110_priv *priv,
> > +				  struct ptp_perout_request perout,
> > +				  int on)
> > +{
> > +	u32 on_nsec;
> > +	u32 phase;
> > +	u32 mask;
> > +	int ret;
> > +
> > +	if (priv->cfg->id == ADIN2111_MAC) {
> > +		ret = phy_clear_bits_mmd(priv->ports[0]->phydev, MDIO_MMD_VEND1,
> > +					 ADIN2111_LED_CNTRL,
> > +					 ADIN2111_LED_CNTRL_LED0_FUNCTION);
> > +		if (ret < 0)
> > +			return ret;
> > +
> > +		ret = phy_set_bits_mmd(priv->ports[0]->phydev, MDIO_MMD_VEND1,
> > +				       ADIN2111_LED_CNTRL,
> > +				       on ? ADIN2111_LED_CNTRL_TS_TIMER : 0);
> 
> I normally say a MAC driver should not be accessing PHY register...
> 
> You have the advantage of knowing it is integrated, so you know
> exactly what PHY it is. But you still have a potential race condition
> sometime in the future. You are not taking the phydev->lock, which is
> something phylib nearly always does before accessing a PHY. If you
> ever add control of the LEDs, that lack of locking could get you in
> trouble.
> 
> Is this functionality always on LED0? It cannot be LED1 or LED2?
> 
>    Andrew

Hi Andrew,

Thanks for the insight. Will add the phylib locking. Device only allows
LED0 pin or INTN pin to be converted to timer output. Can't lose IRQ capability
here so only LED0 could possibly be used.

Thanks,
Alexandru