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Date: Wed, 25 Jan 2023 17:21:48 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Paul Cercueil <paul@...pouillou.net>
Cc: list@...ndingux.net, linux-mips@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Paul Cercueil <paul@...pouillou.net>, stable@...r.kernel.org
Subject: Re: [PATCH] clk: ingenic: jz4760: Update M/N/OD calculation algorithm
Quoting Paul Cercueil (2022-12-14 04:37:04)
> The previous algorithm was pretty broken.
>
> - The inner loop had a '(m > m_max)' condition, and the value of 'm'
> would increase in each iteration;
>
> - Each iteration would actually multiply 'm' by two, so it is not needed
> to re-compute the whole equation at each iteration;
>
> - It would loop until (m & 1) == 0, which means it would loop at most
> once.
>
> - The outer loop would divide the 'n' value by two at the end of each
> iteration. This meant that for a 12 MHz parent clock and a 1.2 GHz
> requested clock, it would first try n=12, then n=6, then n=3, then
> n=1, none of which would work; the only valid value is n=2 in this
> case.
>
> Simplify this algorithm with a single for loop, which decrements 'n'
> after each iteration, addressing all of the above problems.
>
> Fixes: bdbfc029374f ("clk: ingenic: Add support for the JZ4760")
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
> ---
Applied to clk-fixes
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